xref: /linux/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46properties:
47  compatible:
48    oneOf:
49      - items:
50          - enum:
51              - mediatek,mt7986-pcie
52              - mediatek,mt8188-pcie
53              - mediatek,mt8195-pcie
54          - const: mediatek,mt8192-pcie
55      - items:
56          - enum:
57              - mediatek,mt6991-pcie
58          - const: mediatek,mt8196-pcie
59      - const: mediatek,mt8192-pcie
60      - const: mediatek,mt8196-pcie
61      - const: airoha,en7581-pcie
62
63  reg:
64    maxItems: 1
65
66  reg-names:
67    items:
68      - const: pcie-mac
69
70  interrupts:
71    maxItems: 1
72
73  ranges:
74    minItems: 1
75    maxItems: 8
76
77  iommu-map:
78    maxItems: 1
79
80  iommu-map-mask:
81    const: 0
82
83  resets:
84    minItems: 1
85    maxItems: 3
86
87  reset-names:
88    minItems: 1
89    maxItems: 3
90    items:
91      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
92
93  clocks:
94    minItems: 1
95    maxItems: 6
96
97  clock-names:
98    minItems: 1
99    maxItems: 6
100
101  assigned-clocks:
102    maxItems: 1
103
104  assigned-clock-parents:
105    maxItems: 1
106
107  phys:
108    maxItems: 1
109
110  phy-names:
111    items:
112      - const: pcie-phy
113
114  power-domains:
115    maxItems: 1
116
117  mediatek,pbus-csr:
118    $ref: /schemas/types.yaml#/definitions/phandle-array
119    items:
120      - items:
121          - description: phandle to pbus-csr syscon
122          - description: offset of pbus-csr base address register
123          - description: offset of pbus-csr base address mask register
124    description:
125      Phandle with two arguments to the syscon node used to detect if
126      a given address is accessible on PCIe controller.
127
128  '#interrupt-cells':
129    const: 1
130
131  interrupt-controller:
132    description: Interrupt controller node for handling legacy PCI interrupts.
133    type: object
134    properties:
135      '#address-cells':
136        const: 0
137      '#interrupt-cells':
138        const: 1
139      interrupt-controller: true
140
141    required:
142      - '#address-cells'
143      - '#interrupt-cells'
144      - interrupt-controller
145
146    additionalProperties: false
147
148required:
149  - compatible
150  - reg
151  - reg-names
152  - interrupts
153  - ranges
154  - clocks
155  - clock-names
156  - '#interrupt-cells'
157  - interrupt-controller
158
159allOf:
160  - $ref: /schemas/pci/pci-host-bridge.yaml#
161  - if:
162      properties:
163        compatible:
164          const: mediatek,mt8192-pcie
165    then:
166      properties:
167        clocks:
168          minItems: 6
169
170        clock-names:
171          items:
172            - const: pl_250m
173            - const: tl_26m
174            - const: tl_96m
175            - const: tl_32k
176            - const: peri_26m
177            - const: top_133m
178
179        resets:
180          minItems: 1
181          maxItems: 2
182
183        reset-names:
184          minItems: 1
185          maxItems: 2
186
187        mediatek,pbus-csr: false
188
189  - if:
190      properties:
191        compatible:
192          contains:
193            enum:
194              - mediatek,mt8188-pcie
195              - mediatek,mt8195-pcie
196    then:
197      properties:
198        clocks:
199          minItems: 6
200
201        clock-names:
202          items:
203            - const: pl_250m
204            - const: tl_26m
205            - const: tl_96m
206            - const: tl_32k
207            - const: peri_26m
208            - const: peri_mem
209
210        resets:
211          minItems: 1
212          maxItems: 2
213
214        reset-names:
215          minItems: 1
216          maxItems: 2
217
218        mediatek,pbus-csr: false
219
220  - if:
221      properties:
222        compatible:
223          contains:
224            enum:
225              - mediatek,mt8196-pcie
226    then:
227      properties:
228        clocks:
229          minItems: 6
230
231        clock-names:
232          items:
233            - const: pl_250m
234            - const: tl_26m
235            - const: bus
236            - const: low_power
237            - const: peri_26m
238            - const: peri_mem
239
240        resets:
241          minItems: 2
242
243        reset-names:
244          items:
245            - const: phy
246            - const: mac
247
248        mediatek,pbus-csr: false
249
250  - if:
251      properties:
252        compatible:
253          contains:
254            enum:
255              - mediatek,mt7986-pcie
256    then:
257      properties:
258        clocks:
259          minItems: 4
260          maxItems: 4
261
262        clock-names:
263          items:
264            - const: pl_250m
265            - const: tl_26m
266            - const: peri_26m
267            - const: top_133m
268
269        resets:
270          minItems: 1
271          maxItems: 2
272
273        reset-names:
274          minItems: 1
275          maxItems: 2
276
277        mediatek,pbus-csr: false
278
279  - if:
280      properties:
281        compatible:
282          const: airoha,en7581-pcie
283    then:
284      properties:
285        clocks:
286          maxItems: 1
287
288        clock-names:
289          items:
290            - const: sys-ck
291
292        resets:
293          minItems: 3
294
295        reset-names:
296          items:
297            - const: phy-lane0
298            - const: phy-lane1
299            - const: phy-lane2
300
301unevaluatedProperties: false
302
303examples:
304  - |
305    #include <dt-bindings/interrupt-controller/arm-gic.h>
306    #include <dt-bindings/interrupt-controller/irq.h>
307
308    bus {
309        #address-cells = <2>;
310        #size-cells = <2>;
311
312        pcie: pcie@11230000 {
313            compatible = "mediatek,mt8192-pcie";
314            device_type = "pci";
315            #address-cells = <3>;
316            #size-cells = <2>;
317            reg = <0x00 0x11230000 0x00 0x4000>;
318            reg-names = "pcie-mac";
319            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
320            bus-range = <0x00 0xff>;
321            ranges = <0x82000000 0x00 0x12000000 0x00
322                      0x12000000 0x00 0x1000000>;
323            clocks = <&infracfg 44>,
324                     <&infracfg 40>,
325                     <&infracfg 43>,
326                     <&infracfg 97>,
327                     <&infracfg 99>,
328                     <&infracfg 111>;
329            clock-names = "pl_250m", "tl_26m", "tl_96m",
330                          "tl_32k", "peri_26m", "top_133m";
331            assigned-clocks = <&topckgen 50>;
332            assigned-clock-parents = <&topckgen 91>;
333
334            phys = <&pciephy>;
335            phy-names = "pcie-phy";
336
337            resets = <&infracfg_rst 2>,
338                     <&infracfg_rst 3>;
339            reset-names = "phy", "mac";
340
341            #interrupt-cells = <1>;
342            interrupt-map-mask = <0 0 0 0x7>;
343            interrupt-map = <0 0 0 1 &pcie_intc 0>,
344                            <0 0 0 2 &pcie_intc 1>,
345                            <0 0 0 3 &pcie_intc 2>,
346                            <0 0 0 4 &pcie_intc 3>;
347            pcie_intc: interrupt-controller {
348                      #address-cells = <0>;
349                      #interrupt-cells = <1>;
350                      interrupt-controller;
351            };
352        };
353    };
354