xref: /linux/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml (revision 184e56e77c06a7eef68a021e9d4b11a11a8ab096) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46properties:
47  compatible:
48    oneOf:
49      - items:
50          - enum:
51              - mediatek,mt7986-pcie
52              - mediatek,mt8188-pcie
53              - mediatek,mt8195-pcie
54          - const: mediatek,mt8192-pcie
55      - const: mediatek,mt8192-pcie
56      - const: airoha,en7581-pcie
57
58  reg:
59    maxItems: 1
60
61  reg-names:
62    items:
63      - const: pcie-mac
64
65  interrupts:
66    maxItems: 1
67
68  ranges:
69    minItems: 1
70    maxItems: 8
71
72  iommu-map:
73    maxItems: 1
74
75  iommu-map-mask:
76    const: 0
77
78  resets:
79    minItems: 1
80    maxItems: 3
81
82  reset-names:
83    minItems: 1
84    maxItems: 3
85    items:
86      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
87
88  clocks:
89    minItems: 1
90    maxItems: 6
91
92  clock-names:
93    minItems: 1
94    maxItems: 6
95
96  assigned-clocks:
97    maxItems: 1
98
99  assigned-clock-parents:
100    maxItems: 1
101
102  phys:
103    maxItems: 1
104
105  phy-names:
106    items:
107      - const: pcie-phy
108
109  power-domains:
110    maxItems: 1
111
112  mediatek,pbus-csr:
113    $ref: /schemas/types.yaml#/definitions/phandle-array
114    items:
115      - items:
116          - description: phandle to pbus-csr syscon
117          - description: offset of pbus-csr base address register
118          - description: offset of pbus-csr base address mask register
119    description:
120      Phandle with two arguments to the syscon node used to detect if
121      a given address is accessible on PCIe controller.
122
123  '#interrupt-cells':
124    const: 1
125
126  interrupt-controller:
127    description: Interrupt controller node for handling legacy PCI interrupts.
128    type: object
129    properties:
130      '#address-cells':
131        const: 0
132      '#interrupt-cells':
133        const: 1
134      interrupt-controller: true
135
136    required:
137      - '#address-cells'
138      - '#interrupt-cells'
139      - interrupt-controller
140
141    additionalProperties: false
142
143required:
144  - compatible
145  - reg
146  - reg-names
147  - interrupts
148  - ranges
149  - clocks
150  - clock-names
151  - '#interrupt-cells'
152  - interrupt-controller
153
154allOf:
155  - $ref: /schemas/pci/pci-host-bridge.yaml#
156  - if:
157      properties:
158        compatible:
159          const: mediatek,mt8192-pcie
160    then:
161      properties:
162        clocks:
163          minItems: 6
164
165        clock-names:
166          items:
167            - const: pl_250m
168            - const: tl_26m
169            - const: tl_96m
170            - const: tl_32k
171            - const: peri_26m
172            - const: top_133m
173
174        resets:
175          minItems: 1
176          maxItems: 2
177
178        reset-names:
179          minItems: 1
180          maxItems: 2
181
182        mediatek,pbus-csr: false
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - mediatek,mt8188-pcie
190              - mediatek,mt8195-pcie
191    then:
192      properties:
193        clocks:
194          minItems: 6
195
196        clock-names:
197          items:
198            - const: pl_250m
199            - const: tl_26m
200            - const: tl_96m
201            - const: tl_32k
202            - const: peri_26m
203            - const: peri_mem
204
205        resets:
206          minItems: 1
207          maxItems: 2
208
209        reset-names:
210          minItems: 1
211          maxItems: 2
212
213        mediatek,pbus-csr: false
214
215  - if:
216      properties:
217        compatible:
218          contains:
219            enum:
220              - mediatek,mt7986-pcie
221    then:
222      properties:
223        clocks:
224          minItems: 4
225          maxItems: 4
226
227        clock-names:
228          items:
229            - const: pl_250m
230            - const: tl_26m
231            - const: peri_26m
232            - const: top_133m
233
234        resets:
235          minItems: 1
236          maxItems: 2
237
238        reset-names:
239          minItems: 1
240          maxItems: 2
241
242        mediatek,pbus-csr: false
243
244  - if:
245      properties:
246        compatible:
247          const: airoha,en7581-pcie
248    then:
249      properties:
250        clocks:
251          maxItems: 1
252
253        clock-names:
254          items:
255            - const: sys-ck
256
257        resets:
258          minItems: 3
259
260        reset-names:
261          items:
262            - const: phy-lane0
263            - const: phy-lane1
264            - const: phy-lane2
265
266unevaluatedProperties: false
267
268examples:
269  - |
270    #include <dt-bindings/interrupt-controller/arm-gic.h>
271    #include <dt-bindings/interrupt-controller/irq.h>
272
273    bus {
274        #address-cells = <2>;
275        #size-cells = <2>;
276
277        pcie: pcie@11230000 {
278            compatible = "mediatek,mt8192-pcie";
279            device_type = "pci";
280            #address-cells = <3>;
281            #size-cells = <2>;
282            reg = <0x00 0x11230000 0x00 0x4000>;
283            reg-names = "pcie-mac";
284            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
285            bus-range = <0x00 0xff>;
286            ranges = <0x82000000 0x00 0x12000000 0x00
287                      0x12000000 0x00 0x1000000>;
288            clocks = <&infracfg 44>,
289                     <&infracfg 40>,
290                     <&infracfg 43>,
291                     <&infracfg 97>,
292                     <&infracfg 99>,
293                     <&infracfg 111>;
294            clock-names = "pl_250m", "tl_26m", "tl_96m",
295                          "tl_32k", "peri_26m", "top_133m";
296            assigned-clocks = <&topckgen 50>;
297            assigned-clock-parents = <&topckgen 91>;
298
299            phys = <&pciephy>;
300            phy-names = "pcie-phy";
301
302            resets = <&infracfg_rst 2>,
303                     <&infracfg_rst 3>;
304            reset-names = "phy", "mac";
305
306            #interrupt-cells = <1>;
307            interrupt-map-mask = <0 0 0 0x7>;
308            interrupt-map = <0 0 0 1 &pcie_intc 0>,
309                            <0 0 0 2 &pcie_intc 1>,
310                            <0 0 0 3 &pcie_intc 2>,
311                            <0 0 0 4 &pcie_intc 3>;
312            pcie_intc: interrupt-controller {
313                      #address-cells = <0>;
314                      #interrupt-cells = <1>;
315                      interrupt-controller;
316            };
317        };
318    };
319