xref: /linux/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml (revision c5288cda69ee2d8607f5026bd599a5cebf0ee783) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek MT7621 PCIe controller
8
9maintainers:
10  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12description: |+
13  MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14  with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
15
16allOf:
17  - $ref: /schemas/pci/pci-host-bridge.yaml#
18
19properties:
20  compatible:
21    const: mediatek,mt7621-pci
22
23  reg:
24    items:
25      - description: host-pci bridge registers
26      - description: pcie port 0 RC control registers
27      - description: pcie port 1 RC control registers
28      - description: pcie port 2 RC control registers
29
30  ranges:
31    maxItems: 2
32
33patternProperties:
34  '^pcie@[0-2],0$':
35    type: object
36    $ref: /schemas/pci/pci-pci-bridge.yaml#
37
38    properties:
39      reg:
40        maxItems: 1
41
42      resets:
43        maxItems: 1
44
45      clocks:
46        maxItems: 1
47
48      phys:
49        maxItems: 1
50
51      phy-names:
52        pattern: '^pcie-phy[0-2]$'
53
54    required:
55      - "#interrupt-cells"
56      - interrupt-map-mask
57      - interrupt-map
58      - resets
59      - clocks
60      - phys
61      - phy-names
62      - ranges
63
64    unevaluatedProperties: false
65
66required:
67  - compatible
68  - reg
69  - ranges
70  - "#interrupt-cells"
71  - interrupt-map-mask
72  - interrupt-map
73  - reset-gpios
74
75unevaluatedProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/gpio/gpio.h>
80    #include <dt-bindings/interrupt-controller/mips-gic.h>
81
82    pcie: pcie@1e140000 {
83        compatible = "mediatek,mt7621-pci";
84        reg = <0x1e140000 0x100>,
85              <0x1e142000 0x100>,
86              <0x1e143000 0x100>,
87              <0x1e144000 0x100>;
88
89        #address-cells = <3>;
90        #size-cells = <2>;
91        pinctrl-names = "default";
92        pinctrl-0 = <&pcie_pins>;
93        device_type = "pci";
94        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
95                 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
96        #interrupt-cells = <1>;
97        interrupt-map-mask = <0xF800 0 0 0>;
98        interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
99                        <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
100                        <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
101        reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
102
103        pcie@0,0 {
104            reg = <0x0000 0 0 0 0>;
105            #address-cells = <3>;
106            #size-cells = <2>;
107            device_type = "pci";
108            #interrupt-cells = <1>;
109            interrupt-map-mask = <0 0 0 0>;
110            interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
111            resets = <&rstctrl 24>;
112            clocks = <&clkctrl 24>;
113            phys = <&pcie0_phy 1>;
114            phy-names = "pcie-phy0";
115            ranges;
116        };
117
118        pcie@1,0 {
119            reg = <0x0800 0 0 0 0>;
120            #address-cells = <3>;
121            #size-cells = <2>;
122            device_type = "pci";
123            #interrupt-cells = <1>;
124            interrupt-map-mask = <0 0 0 0>;
125            interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
126            resets = <&rstctrl 25>;
127            clocks = <&clkctrl 25>;
128            phys = <&pcie0_phy 1>;
129            phy-names = "pcie-phy1";
130            ranges;
131        };
132
133        pcie@2,0 {
134            reg = <0x1000 0 0 0 0>;
135            #address-cells = <3>;
136            #size-cells = <2>;
137            device_type = "pci";
138            #interrupt-cells = <1>;
139            interrupt-map-mask = <0 0 0 0>;
140            interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
141            resets = <&rstctrl 26>;
142            clocks = <&clkctrl 26>;
143            phys = <&pcie2_phy 0>;
144            phy-names = "pcie-phy2";
145            ranges;
146        };
147    };
148...
149