xref: /linux/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml (revision 4b3c1f1b15f576445c221cbc77a88540433a2ba7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PCIe RC controller on Intel Gateway SoCs
8
9maintainers:
10  - Dilip Kota <eswara.kota@linux.intel.com>
11
12properties:
13  compatible:
14    items:
15      - const: intel,lgm-pcie
16      - const: snps,dw-pcie
17
18  device_type:
19    const: pci
20
21  "#address-cells":
22    const: 3
23
24  "#size-cells":
25    const: 2
26
27  reg:
28    items:
29      - description: Controller control and status registers.
30      - description: PCIe configuration registers.
31      - description: Controller application registers.
32
33  reg-names:
34    items:
35      - const: dbi
36      - const: config
37      - const: app
38
39  ranges:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45  clocks:
46    maxItems: 1
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    const: pcie
53
54  reset-gpios:
55    maxItems: 1
56
57  linux,pci-domain: true
58
59  num-lanes:
60    maximum: 2
61    description: Number of lanes to use for this port.
62
63  '#interrupt-cells':
64    const: 1
65
66  interrupt-map-mask:
67    description: Standard PCI IRQ mapping properties.
68
69  interrupt-map:
70    description: Standard PCI IRQ mapping properties.
71
72  max-link-speed:
73    description: Specify PCI Gen for link capability.
74    $ref: /schemas/types.yaml#/definitions/uint32
75    enum: [1, 2, 3, 4]
76    default: 1
77
78  bus-range:
79    description: Range of bus numbers associated with this controller.
80
81  reset-assert-ms:
82    description: |
83      Delay after asserting reset to the PCIe device.
84    maximum: 500
85    default: 100
86
87required:
88  - compatible
89  - device_type
90  - "#address-cells"
91  - "#size-cells"
92  - reg
93  - reg-names
94  - ranges
95  - resets
96  - clocks
97  - phys
98  - phy-names
99  - reset-gpios
100  - '#interrupt-cells'
101  - interrupt-map
102  - interrupt-map-mask
103
104additionalProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/gpio/gpio.h>
109    pcie10: pcie@d0e00000 {
110      compatible = "intel,lgm-pcie", "snps,dw-pcie";
111      device_type = "pci";
112      #address-cells = <3>;
113      #size-cells = <2>;
114      reg = <0xd0e00000 0x1000>,
115            <0xd2000000 0x800000>,
116            <0xd0a41000 0x1000>;
117      reg-names = "dbi", "config", "app";
118      linux,pci-domain = <0>;
119      max-link-speed = <4>;
120      bus-range = <0x00 0x08>;
121      #interrupt-cells = <1>;
122      interrupt-map-mask = <0 0 0 0x7>;
123      interrupt-map = <0 0 0 1 &ioapic1 27 1>,
124                      <0 0 0 2 &ioapic1 28 1>,
125                      <0 0 0 3 &ioapic1 29 1>,
126                      <0 0 0 4 &ioapic1 30 1>;
127      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
128      resets = <&rcu0 0x50 0>;
129      clocks = <&cgu0 120>;
130      phys = <&cb0phy0>;
131      phy-names = "pcie";
132      reset-assert-ms = <500>;
133      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
134      num-lanes = <2>;
135    };
136