xref: /linux/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml (revision 1959ba4e40ce40c380dbe868433f5c4b20bb1ba3) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PCIe RC controller on Intel Gateway SoCs
8
9maintainers:
10  - Dilip Kota <eswara.kota@linux.intel.com>
11
12select:
13  properties:
14    compatible:
15      contains:
16        const: intel,lgm-pcie
17  required:
18    - compatible
19
20properties:
21  compatible:
22    items:
23      - const: intel,lgm-pcie
24      - const: snps,dw-pcie
25
26  device_type:
27    const: pci
28
29  "#address-cells":
30    const: 3
31
32  "#size-cells":
33    const: 2
34
35  reg:
36    items:
37      - description: Controller control and status registers.
38      - description: PCIe configuration registers.
39      - description: Controller application registers.
40
41  reg-names:
42    items:
43      - const: dbi
44      - const: config
45      - const: app
46
47  ranges:
48    maxItems: 1
49
50  resets:
51    maxItems: 1
52
53  clocks:
54    maxItems: 1
55
56  phys:
57    maxItems: 1
58
59  phy-names:
60    const: pcie
61
62  reset-gpios:
63    maxItems: 1
64
65  linux,pci-domain: true
66
67  num-lanes:
68    maximum: 2
69    description: Number of lanes to use for this port.
70
71  '#interrupt-cells':
72    const: 1
73
74  interrupt-map-mask:
75    description: Standard PCI IRQ mapping properties.
76
77  interrupt-map:
78    description: Standard PCI IRQ mapping properties.
79
80  max-link-speed:
81    description: Specify PCI Gen for link capability.
82    $ref: /schemas/types.yaml#/definitions/uint32
83    enum: [1, 2, 3, 4]
84    default: 1
85
86  bus-range:
87    description: Range of bus numbers associated with this controller.
88
89  reset-assert-ms:
90    description: |
91      Delay after asserting reset to the PCIe device.
92    maximum: 500
93    default: 100
94
95required:
96  - compatible
97  - device_type
98  - "#address-cells"
99  - "#size-cells"
100  - reg
101  - reg-names
102  - ranges
103  - resets
104  - clocks
105  - phys
106  - phy-names
107  - reset-gpios
108  - '#interrupt-cells'
109  - interrupt-map
110  - interrupt-map-mask
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/gpio/gpio.h>
117    pcie10: pcie@d0e00000 {
118      compatible = "intel,lgm-pcie", "snps,dw-pcie";
119      device_type = "pci";
120      #address-cells = <3>;
121      #size-cells = <2>;
122      reg = <0xd0e00000 0x1000>,
123            <0xd2000000 0x800000>,
124            <0xd0a41000 0x1000>;
125      reg-names = "dbi", "config", "app";
126      linux,pci-domain = <0>;
127      max-link-speed = <4>;
128      bus-range = <0x00 0x08>;
129      #interrupt-cells = <1>;
130      interrupt-map-mask = <0 0 0 0x7>;
131      interrupt-map = <0 0 0 1 &ioapic1 27 1>,
132                      <0 0 0 2 &ioapic1 28 1>,
133                      <0 0 0 3 &ioapic1 29 1>,
134                      <0 0 0 4 &ioapic1 30 1>;
135      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
136      resets = <&rcu0 0x50 0>;
137      clocks = <&cgu0 120>;
138      phys = <&cb0phy0>;
139      phy-names = "pcie";
140      reset-assert-ms = <500>;
141      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
142      num-lanes = <2>;
143    };
144