1ace5219fSLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ace5219fSLinus Walleij%YAML 1.2 3ace5219fSLinus Walleij--- 4ace5219fSLinus Walleij$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml# 5ace5219fSLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 6ace5219fSLinus Walleij 7ace5219fSLinus Walleijtitle: Intel IXP4xx PCI controller 8ace5219fSLinus Walleij 9ace5219fSLinus Walleijmaintainers: 10ace5219fSLinus Walleij - Linus Walleij <linus.walleij@linaro.org> 11ace5219fSLinus Walleij 12ace5219fSLinus Walleijdescription: PCI host controller found in the Intel IXP4xx SoC series. 13ace5219fSLinus Walleij 14ace5219fSLinus WalleijallOf: 15*5db62b7dSKrzysztof Kozlowski - $ref: /schemas/pci/pci-host-bridge.yaml# 16ace5219fSLinus Walleij 17ace5219fSLinus Walleijproperties: 18ace5219fSLinus Walleij compatible: 19ace5219fSLinus Walleij items: 20ace5219fSLinus Walleij - enum: 21ace5219fSLinus Walleij - intel,ixp42x-pci 22ace5219fSLinus Walleij - intel,ixp43x-pci 23ace5219fSLinus Walleij description: The two supported variants are ixp42x and ixp43x, 24ace5219fSLinus Walleij though more variants may exist. 25ace5219fSLinus Walleij 26ace5219fSLinus Walleij reg: 27ace5219fSLinus Walleij items: 28ace5219fSLinus Walleij - description: IXP4xx-specific registers 29ace5219fSLinus Walleij 30ace5219fSLinus Walleij interrupts: 31ace5219fSLinus Walleij items: 32ace5219fSLinus Walleij - description: Main PCI interrupt 33ace5219fSLinus Walleij - description: PCI DMA interrupt 1 34ace5219fSLinus Walleij - description: PCI DMA interrupt 2 35ace5219fSLinus Walleij 36ace5219fSLinus Walleij ranges: 37ace5219fSLinus Walleij maxItems: 2 38ace5219fSLinus Walleij description: Typically one memory range of 64MB and one IO 39ace5219fSLinus Walleij space range of 64KB. 40ace5219fSLinus Walleij 41ace5219fSLinus Walleij dma-ranges: 42ace5219fSLinus Walleij maxItems: 1 43ace5219fSLinus Walleij description: The DMA range tells the PCI host which addresses 44ace5219fSLinus Walleij the RAM is at. It can map only 64MB so if the RAM is bigger 45ace5219fSLinus Walleij than 64MB the DMA access has to be restricted to these 46ace5219fSLinus Walleij addresses. 47ace5219fSLinus Walleij 48ace5219fSLinus Walleij "#interrupt-cells": true 49ace5219fSLinus Walleij 50ace5219fSLinus Walleij interrupt-map: true 51ace5219fSLinus Walleij 52ace5219fSLinus Walleij interrupt-map-mask: 53ace5219fSLinus Walleij items: 54ace5219fSLinus Walleij - const: 0xf800 55ace5219fSLinus Walleij - const: 0 56ace5219fSLinus Walleij - const: 0 57ace5219fSLinus Walleij - const: 7 58ace5219fSLinus Walleij 59ace5219fSLinus Walleijrequired: 60ace5219fSLinus Walleij - compatible 61ace5219fSLinus Walleij - reg 62ace5219fSLinus Walleij - dma-ranges 63ace5219fSLinus Walleij - "#interrupt-cells" 64ace5219fSLinus Walleij - interrupt-map 65ace5219fSLinus Walleij - interrupt-map-mask 66ace5219fSLinus Walleij 67ace5219fSLinus WalleijunevaluatedProperties: false 68ace5219fSLinus Walleij 69ace5219fSLinus Walleijexamples: 70ace5219fSLinus Walleij - | 71ace5219fSLinus Walleij pci@c0000000 { 72ace5219fSLinus Walleij compatible = "intel,ixp43x-pci"; 73ace5219fSLinus Walleij reg = <0xc0000000 0x1000>; 74ace5219fSLinus Walleij #address-cells = <3>; 75ace5219fSLinus Walleij #size-cells = <2>; 76ace5219fSLinus Walleij device_type = "pci"; 77ace5219fSLinus Walleij bus-range = <0x00 0xff>; 78ace5219fSLinus Walleij 79ace5219fSLinus Walleij ranges = 80ace5219fSLinus Walleij <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, 81ace5219fSLinus Walleij <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; 82ace5219fSLinus Walleij dma-ranges = 83ace5219fSLinus Walleij <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 84ace5219fSLinus Walleij 85ace5219fSLinus Walleij #interrupt-cells = <1>; 86ace5219fSLinus Walleij interrupt-map-mask = <0xf800 0 0 7>; 87ace5219fSLinus Walleij interrupt-map = 88ace5219fSLinus Walleij <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ 89ace5219fSLinus Walleij <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ 90ace5219fSLinus Walleij <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ 91ace5219fSLinus Walleij <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ 92ace5219fSLinus Walleij <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ 93ace5219fSLinus Walleij <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ 94ace5219fSLinus Walleij <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ 95ace5219fSLinus Walleij <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ 96ace5219fSLinus Walleij <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ 97ace5219fSLinus Walleij <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ 98ace5219fSLinus Walleij <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ 99ace5219fSLinus Walleij <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */ 100ace5219fSLinus Walleij }; 101