1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Layerscape PCIe Root Complex(RC) controller 8 9maintainers: 10 - Frank Li <Frank.Li@nxp.com> 11 12description: 13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP 14 15 This controller derives its clocks from the Reset Configuration Word (RCW) 16 which is used to describe the PLL settings at the time of chip-reset. 17 18 Also as per the available Reference Manuals, there is no specific 'version' 19 register available in the Freescale PCIe controller register set, 20 which can allow determining the underlying DesignWare PCIe controller version 21 information. 22 23properties: 24 compatible: 25 enum: 26 - fsl,ls1021a-pcie 27 - fsl,ls2080a-pcie 28 - fsl,ls2085a-pcie 29 - fsl,ls2088a-pcie 30 - fsl,ls1088a-pcie 31 - fsl,ls1046a-pcie 32 - fsl,ls1043a-pcie 33 - fsl,ls1012a-pcie 34 - fsl,ls1028a-pcie 35 - fsl,lx2160a-pcie 36 37 reg: 38 maxItems: 2 39 40 reg-names: 41 items: 42 - const: regs 43 - const: config 44 45 fsl,pcie-scfg: 46 $ref: /schemas/types.yaml#/definitions/phandle 47 description: A phandle to the SCFG device node. The second entry is the 48 physical PCIe controller index starting from '0'. This is used to get 49 SCFG PEXN registers. 50 51 big-endian: 52 $ref: /schemas/types.yaml#/definitions/flag 53 description: If the PEX_LUT and PF register block is in big-endian, specify 54 this property. 55 56 dma-coherent: true 57 58 msi-parent: true 59 60 iommu-map: true 61 62 interrupts: 63 minItems: 1 64 maxItems: 2 65 66 interrupt-names: 67 minItems: 1 68 maxItems: 2 69 70required: 71 - compatible 72 - reg 73 - reg-names 74 - "#address-cells" 75 - "#size-cells" 76 - device_type 77 - bus-range 78 - ranges 79 - interrupts 80 - interrupt-names 81 - "#interrupt-cells" 82 - interrupt-map-mask 83 - interrupt-map 84 85allOf: 86 - $ref: /schemas/pci/pci-bus.yaml# 87 88 - if: 89 properties: 90 compatible: 91 enum: 92 - fsl,ls1028a-pcie 93 - fsl,ls1046a-pcie 94 - fsl,ls1043a-pcie 95 - fsl,ls1012a-pcie 96 then: 97 properties: 98 interrupts: 99 maxItems: 2 100 interrupt-names: 101 items: 102 - const: pme 103 - const: aer 104 105 - if: 106 properties: 107 compatible: 108 enum: 109 - fsl,ls2080a-pcie 110 - fsl,ls2085a-pcie 111 - fsl,ls2088a-pcie 112 then: 113 properties: 114 interrupts: 115 maxItems: 1 116 interrupt-names: 117 items: 118 - const: intr 119 120 - if: 121 properties: 122 compatible: 123 enum: 124 - fsl,ls1088a-pcie 125 then: 126 properties: 127 interrupts: 128 maxItems: 1 129 interrupt-names: 130 items: 131 - const: aer 132 133unevaluatedProperties: false 134 135examples: 136 - | 137 #include <dt-bindings/interrupt-controller/arm-gic.h> 138 139 soc { 140 #address-cells = <2>; 141 #size-cells = <2>; 142 143 pcie@3400000 { 144 compatible = "fsl,ls1088a-pcie"; 145 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 146 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 147 reg-names = "regs", "config"; 148 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 149 interrupt-names = "aer"; 150 #address-cells = <3>; 151 #size-cells = <2>; 152 dma-coherent; 153 device_type = "pci"; 154 bus-range = <0x0 0xff>; 155 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 156 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 157 msi-parent = <&its>; 158 #interrupt-cells = <1>; 159 interrupt-map-mask = <0 0 0 7>; 160 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 161 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 162 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 163 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 164 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 165 }; 166 }; 167... 168