1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX6 PCIe host controller 8 9maintainers: 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 12 13description: |+ 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 16 17properties: 18 compatible: 19 enum: 20 - fsl,imx6q-pcie 21 - fsl,imx6sx-pcie 22 - fsl,imx6qp-pcie 23 - fsl,imx7d-pcie 24 - fsl,imx8mq-pcie 25 - fsl,imx8mm-pcie 26 - fsl,imx8mp-pcie 27 - fsl,imx8mm-pcie-ep 28 - fsl,imx8mq-pcie-ep 29 30 reg: 31 items: 32 - description: Data Bus Interface (DBI) registers. 33 - description: PCIe configuration space region. 34 35 reg-names: 36 items: 37 - const: dbi 38 - const: config 39 40 interrupts: 41 items: 42 - description: builtin MSI controller. 43 44 interrupt-names: 45 items: 46 - const: msi 47 48 clocks: 49 minItems: 3 50 items: 51 - description: PCIe bridge clock. 52 - description: PCIe bus clock. 53 - description: PCIe PHY clock. 54 - description: Additional required clock entry for imx6sx-pcie, 55 imx8mq-pcie. 56 57 clock-names: 58 minItems: 3 59 items: 60 - const: pcie 61 - const: pcie_bus 62 - enum: [ pcie_phy, pcie_aux ] 63 - enum: [ pcie_inbound_axi, pcie_aux ] 64 65 num-lanes: 66 const: 1 67 68 fsl,imx7d-pcie-phy: 69 $ref: /schemas/types.yaml#/definitions/phandle 70 description: A phandle to an fsl,imx7d-pcie-phy node. Additional 71 required properties for imx7d-pcie and imx8mq-pcie. 72 73 power-domains: 74 minItems: 1 75 items: 76 - description: The phandle pointing to the DISPLAY domain for 77 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and 78 imx8mq-pcie. 79 - description: The phandle pointing to the PCIE_PHY power domains 80 for imx6sx-pcie. 81 82 power-domain-names: 83 minItems: 1 84 items: 85 - const: pcie 86 - const: pcie_phy 87 88 resets: 89 minItems: 2 90 maxItems: 3 91 description: Phandles to PCIe-related reset lines exposed by SRC 92 IP block. Additional required by imx7d-pcie and imx8mq-pcie. 93 94 reset-names: 95 minItems: 2 96 maxItems: 3 97 98 fsl,tx-deemph-gen1: 99 description: Gen1 De-emphasis value (optional required). 100 $ref: /schemas/types.yaml#/definitions/uint32 101 default: 0 102 103 fsl,tx-deemph-gen2-3p5db: 104 description: Gen2 (3.5db) De-emphasis value (optional required). 105 $ref: /schemas/types.yaml#/definitions/uint32 106 default: 0 107 108 fsl,tx-deemph-gen2-6db: 109 description: Gen2 (6db) De-emphasis value (optional required). 110 $ref: /schemas/types.yaml#/definitions/uint32 111 default: 20 112 113 fsl,tx-swing-full: 114 description: Gen2 TX SWING FULL value (optional required). 115 $ref: /schemas/types.yaml#/definitions/uint32 116 default: 127 117 118 fsl,tx-swing-low: 119 description: TX launch amplitude swing_low value (optional required). 120 $ref: /schemas/types.yaml#/definitions/uint32 121 default: 127 122 123 fsl,max-link-speed: 124 description: Specify PCI Gen for link capability (optional required). 125 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter 126 requirements and thus for gen2 capability a gen2 compliant clock 127 generator should be used and configured. 128 $ref: /schemas/types.yaml#/definitions/uint32 129 enum: [1, 2, 3, 4] 130 default: 1 131 132 phys: 133 maxItems: 1 134 135 phy-names: 136 const: pcie-phy 137 138 reset-gpio: 139 description: Should specify the GPIO for controlling the PCI bus device 140 reset signal. It's not polarity aware and defaults to active-low reset 141 sequence (L=reset state, H=operation state) (optional required). 142 143 reset-gpio-active-high: 144 description: If present then the reset sequence using the GPIO 145 specified in the "reset-gpio" property is reversed (H=reset state, 146 L=operation state) (optional required). 147 type: boolean 148 149 vpcie-supply: 150 description: Should specify the regulator in charge of PCIe port power. 151 The regulator will be enabled when initializing the PCIe host and 152 disabled either as part of the init process or when shutting down 153 the host (optional required). 154 155 vph-supply: 156 description: Should specify the regulator in charge of VPH one of 157 the three PCIe PHY powers. This regulator can be supplied by both 158 1.8v and 3.3v voltage supplies (optional required). 159 160required: 161 - compatible 162 - reg 163 - reg-names 164 - "#address-cells" 165 - "#size-cells" 166 - device_type 167 - bus-range 168 - ranges 169 - num-lanes 170 - interrupts 171 - interrupt-names 172 - "#interrupt-cells" 173 - interrupt-map-mask 174 - interrupt-map 175 - clocks 176 - clock-names 177 178allOf: 179 - $ref: /schemas/pci/snps,dw-pcie.yaml# 180 - if: 181 properties: 182 compatible: 183 contains: 184 const: fsl,imx6sx-pcie 185 then: 186 properties: 187 clock-names: 188 items: 189 - {} 190 - {} 191 - const: pcie_phy 192 - const: pcie_inbound_axi 193 power-domains: 194 minItems: 2 195 power-domain-names: 196 minItems: 2 197 - if: 198 properties: 199 compatible: 200 contains: 201 const: fsl,imx8mq-pcie 202 then: 203 properties: 204 clock-names: 205 items: 206 - {} 207 - {} 208 - const: pcie_phy 209 - const: pcie_aux 210 - if: 211 properties: 212 compatible: 213 not: 214 contains: 215 enum: 216 - fsl,imx6sx-pcie 217 - fsl,imx8mq-pcie 218 then: 219 properties: 220 clocks: 221 maxItems: 3 222 clock-names: 223 maxItems: 3 224 225 - if: 226 properties: 227 compatible: 228 contains: 229 enum: 230 - fsl,imx6q-pcie 231 - fsl,imx6qp-pcie 232 - fsl,imx7d-pcie 233 then: 234 properties: 235 clock-names: 236 maxItems: 3 237 contains: 238 const: pcie_phy 239 240 - if: 241 properties: 242 compatible: 243 contains: 244 enum: 245 - fsl,imx8mm-pcie 246 - fsl,imx8mp-pcie 247 then: 248 properties: 249 clock-names: 250 maxItems: 3 251 contains: 252 const: pcie_aux 253 - if: 254 properties: 255 compatible: 256 contains: 257 enum: 258 - fsl,imx6q-pcie 259 - fsl,imx6qp-pcie 260 then: 261 properties: 262 power-domains: false 263 power-domain-names: false 264 265 - if: 266 not: 267 properties: 268 compatible: 269 contains: 270 enum: 271 - fsl,imx6sx-pcie 272 - fsl,imx6q-pcie 273 - fsl,imx6qp-pcie 274 then: 275 properties: 276 power-domains: 277 maxItems: 1 278 power-domain-names: false 279 280 - if: 281 properties: 282 compatible: 283 contains: 284 enum: 285 - fsl,imx6q-pcie 286 - fsl,imx6sx-pcie 287 - fsl,imx6qp-pcie 288 - fsl,imx7d-pcie 289 - fsl,imx8mq-pcie 290 then: 291 properties: 292 resets: 293 minItems: 3 294 reset-names: 295 items: 296 - const: pciephy 297 - const: apps 298 - const: turnoff 299 else: 300 properties: 301 resets: 302 maxItems: 2 303 reset-names: 304 items: 305 - const: apps 306 - const: turnoff 307 308unevaluatedProperties: false 309 310examples: 311 - | 312 #include <dt-bindings/clock/imx6qdl-clock.h> 313 #include <dt-bindings/interrupt-controller/arm-gic.h> 314 315 pcie: pcie@1ffc000 { 316 compatible = "fsl,imx6q-pcie"; 317 reg = <0x01ffc000 0x04000>, 318 <0x01f00000 0x80000>; 319 reg-names = "dbi", "config"; 320 #address-cells = <3>; 321 #size-cells = <2>; 322 device_type = "pci"; 323 bus-range = <0x00 0xff>; 324 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, 325 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; 326 num-lanes = <1>; 327 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-names = "msi"; 329 #interrupt-cells = <1>; 330 interrupt-map-mask = <0 0 0 0x7>; 331 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 332 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 333 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 334 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 336 <&clks IMX6QDL_CLK_LVDS1_GATE>, 337 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 338 clock-names = "pcie", "pcie_bus", "pcie_phy"; 339 }; 340... 341