xref: /linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml (revision cecdd52a3dd312564f81a39df08378b7b39a2654) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx6q-pcie
21      - fsl,imx6sx-pcie
22      - fsl,imx6qp-pcie
23      - fsl,imx7d-pcie
24      - fsl,imx8mq-pcie
25      - fsl,imx8mm-pcie
26      - fsl,imx8mp-pcie
27      - fsl,imx8mm-pcie-ep
28      - fsl,imx8mq-pcie-ep
29      - fsl,imx8mp-pcie-ep
30
31  reg:
32    items:
33      - description: Data Bus Interface (DBI) registers.
34      - description: PCIe configuration space region.
35
36  reg-names:
37    items:
38      - const: dbi
39      - const: config
40
41  interrupts:
42    items:
43      - description: builtin MSI controller.
44
45  interrupt-names:
46    items:
47      - const: msi
48
49  clocks:
50    minItems: 3
51    items:
52      - description: PCIe bridge clock.
53      - description: PCIe bus clock.
54      - description: PCIe PHY clock.
55      - description: Additional required clock entry for imx6sx-pcie,
56          imx8mq-pcie.
57
58  clock-names:
59    minItems: 3
60    items:
61      - const: pcie
62      - const: pcie_bus
63      - enum: [ pcie_phy, pcie_aux ]
64      - enum: [ pcie_inbound_axi, pcie_aux ]
65
66  num-lanes:
67    const: 1
68
69  fsl,imx7d-pcie-phy:
70    $ref: /schemas/types.yaml#/definitions/phandle
71    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
72      required properties for imx7d-pcie and imx8mq-pcie.
73
74  power-domains:
75    minItems: 1
76    items:
77      - description: The phandle pointing to the DISPLAY domain for
78          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
79          imx8mq-pcie.
80      - description: The phandle pointing to the PCIE_PHY power domains
81          for imx6sx-pcie.
82
83  power-domain-names:
84    minItems: 1
85    items:
86      - const: pcie
87      - const: pcie_phy
88
89  resets:
90    minItems: 2
91    maxItems: 3
92    description: Phandles to PCIe-related reset lines exposed by SRC
93      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
94
95  reset-names:
96    minItems: 2
97    maxItems: 3
98
99  fsl,tx-deemph-gen1:
100    description: Gen1 De-emphasis value (optional required).
101    $ref: /schemas/types.yaml#/definitions/uint32
102    default: 0
103
104  fsl,tx-deemph-gen2-3p5db:
105    description: Gen2 (3.5db) De-emphasis value (optional required).
106    $ref: /schemas/types.yaml#/definitions/uint32
107    default: 0
108
109  fsl,tx-deemph-gen2-6db:
110    description: Gen2 (6db) De-emphasis value (optional required).
111    $ref: /schemas/types.yaml#/definitions/uint32
112    default: 20
113
114  fsl,tx-swing-full:
115    description: Gen2 TX SWING FULL value (optional required).
116    $ref: /schemas/types.yaml#/definitions/uint32
117    default: 127
118
119  fsl,tx-swing-low:
120    description: TX launch amplitude swing_low value (optional required).
121    $ref: /schemas/types.yaml#/definitions/uint32
122    default: 127
123
124  fsl,max-link-speed:
125    description: Specify PCI Gen for link capability (optional required).
126      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
127      requirements and thus for gen2 capability a gen2 compliant clock
128      generator should be used and configured.
129    $ref: /schemas/types.yaml#/definitions/uint32
130    enum: [1, 2, 3, 4]
131    default: 1
132
133  phys:
134    maxItems: 1
135
136  phy-names:
137    const: pcie-phy
138
139  reset-gpio:
140    description: Should specify the GPIO for controlling the PCI bus device
141      reset signal. It's not polarity aware and defaults to active-low reset
142      sequence (L=reset state, H=operation state) (optional required).
143
144  reset-gpio-active-high:
145    description: If present then the reset sequence using the GPIO
146      specified in the "reset-gpio" property is reversed (H=reset state,
147      L=operation state) (optional required).
148    type: boolean
149
150  vpcie-supply:
151    description: Should specify the regulator in charge of PCIe port power.
152      The regulator will be enabled when initializing the PCIe host and
153      disabled either as part of the init process or when shutting down
154      the host (optional required).
155
156  vph-supply:
157    description: Should specify the regulator in charge of VPH one of
158      the three PCIe PHY powers. This regulator can be supplied by both
159      1.8v and 3.3v voltage supplies (optional required).
160
161required:
162  - compatible
163  - reg
164  - reg-names
165  - "#address-cells"
166  - "#size-cells"
167  - device_type
168  - bus-range
169  - ranges
170  - num-lanes
171  - interrupts
172  - interrupt-names
173  - "#interrupt-cells"
174  - interrupt-map-mask
175  - interrupt-map
176  - clocks
177  - clock-names
178
179allOf:
180  - $ref: /schemas/pci/snps,dw-pcie.yaml#
181  - if:
182      properties:
183        compatible:
184          contains:
185            const: fsl,imx6sx-pcie
186    then:
187      properties:
188        clock-names:
189          items:
190            - {}
191            - {}
192            - const: pcie_phy
193            - const: pcie_inbound_axi
194        power-domains:
195          minItems: 2
196        power-domain-names:
197          minItems: 2
198  - if:
199      properties:
200        compatible:
201          contains:
202            const: fsl,imx8mq-pcie
203    then:
204      properties:
205        clock-names:
206          items:
207            - {}
208            - {}
209            - const: pcie_phy
210            - const: pcie_aux
211  - if:
212      properties:
213        compatible:
214          not:
215            contains:
216              enum:
217                - fsl,imx6sx-pcie
218                - fsl,imx8mq-pcie
219    then:
220      properties:
221        clocks:
222          maxItems: 3
223        clock-names:
224          maxItems: 3
225
226  - if:
227      properties:
228        compatible:
229          contains:
230            enum:
231              - fsl,imx6q-pcie
232              - fsl,imx6qp-pcie
233              - fsl,imx7d-pcie
234    then:
235      properties:
236        clock-names:
237          maxItems: 3
238          contains:
239            const: pcie_phy
240
241  - if:
242      properties:
243        compatible:
244          contains:
245            enum:
246              - fsl,imx8mm-pcie
247              - fsl,imx8mp-pcie
248    then:
249      properties:
250        clock-names:
251          maxItems: 3
252          contains:
253            const: pcie_aux
254  - if:
255      properties:
256        compatible:
257          contains:
258            enum:
259              - fsl,imx6q-pcie
260              - fsl,imx6qp-pcie
261    then:
262      properties:
263        power-domains: false
264        power-domain-names: false
265
266  - if:
267      not:
268        properties:
269          compatible:
270            contains:
271              enum:
272                - fsl,imx6sx-pcie
273                - fsl,imx6q-pcie
274                - fsl,imx6qp-pcie
275    then:
276      properties:
277        power-domains:
278          maxItems: 1
279        power-domain-names: false
280
281  - if:
282      properties:
283        compatible:
284          contains:
285            enum:
286              - fsl,imx6q-pcie
287              - fsl,imx6sx-pcie
288              - fsl,imx6qp-pcie
289              - fsl,imx7d-pcie
290              - fsl,imx8mq-pcie
291    then:
292      properties:
293        resets:
294          minItems: 3
295        reset-names:
296          items:
297            - const: pciephy
298            - const: apps
299            - const: turnoff
300    else:
301      properties:
302        resets:
303          maxItems: 2
304        reset-names:
305          items:
306            - const: apps
307            - const: turnoff
308
309unevaluatedProperties: false
310
311examples:
312  - |
313    #include <dt-bindings/clock/imx6qdl-clock.h>
314    #include <dt-bindings/interrupt-controller/arm-gic.h>
315
316    pcie: pcie@1ffc000 {
317        compatible = "fsl,imx6q-pcie";
318        reg = <0x01ffc000 0x04000>,
319              <0x01f00000 0x80000>;
320        reg-names = "dbi", "config";
321        #address-cells = <3>;
322        #size-cells = <2>;
323        device_type = "pci";
324        bus-range = <0x00 0xff>;
325        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
326                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
327        num-lanes = <1>;
328        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
329        interrupt-names = "msi";
330        #interrupt-cells = <1>;
331        interrupt-map-mask = <0 0 0 0x7>;
332        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
333                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
334                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
335                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
336        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
337                <&clks IMX6QDL_CLK_LVDS1_GATE>,
338                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
339        clock-names = "pcie", "pcie_bus", "pcie_phy";
340    };
341...
342