xref: /linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml (revision 705c1da8fa4816fb0159b5602fef1df5946a3ee2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16  The controller instances are dual mode where in they can work either in
17  Root Port mode or Endpoint mode but one at a time.
18
19  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20  bindings.
21
22properties:
23  compatible:
24    enum:
25      - fsl,imx6q-pcie
26      - fsl,imx6sx-pcie
27      - fsl,imx6qp-pcie
28      - fsl,imx7d-pcie
29      - fsl,imx8mq-pcie
30      - fsl,imx8mm-pcie
31      - fsl,imx8mp-pcie
32      - fsl,imx95-pcie
33
34  clocks:
35    minItems: 3
36    items:
37      - description: PCIe bridge clock.
38      - description: PCIe bus clock.
39      - description: PCIe PHY clock.
40      - description: Additional required clock entry for imx6sx-pcie,
41           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
42
43  clock-names:
44    minItems: 3
45    maxItems: 4
46
47  interrupts:
48    items:
49      - description: builtin MSI controller.
50
51  interrupt-names:
52    items:
53      - const: msi
54
55  reset-gpio:
56    description: Should specify the GPIO for controlling the PCI bus device
57      reset signal. It's not polarity aware and defaults to active-low reset
58      sequence (L=reset state, H=operation state) (optional required).
59
60  reset-gpio-active-high:
61    description: If present then the reset sequence using the GPIO
62      specified in the "reset-gpio" property is reversed (H=reset state,
63      L=operation state) (optional required).
64    type: boolean
65
66required:
67  - compatible
68  - reg
69  - reg-names
70  - "#address-cells"
71  - "#size-cells"
72  - device_type
73  - bus-range
74  - ranges
75  - interrupts
76  - interrupt-names
77  - "#interrupt-cells"
78  - interrupt-map-mask
79  - interrupt-map
80
81allOf:
82  - $ref: /schemas/pci/snps,dw-pcie.yaml#
83  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
84  - if:
85      properties:
86        compatible:
87          enum:
88            - fsl,imx6q-pcie
89            - fsl,imx6sx-pcie
90            - fsl,imx6qp-pcie
91            - fsl,imx7d-pcie
92            - fsl,imx8mq-pcie
93            - fsl,imx8mm-pcie
94            - fsl,imx8mp-pcie
95    then:
96      properties:
97        reg:
98          maxItems: 2
99        reg-names:
100          items:
101            - const: dbi
102            - const: config
103
104  - if:
105      properties:
106        compatible:
107          enum:
108            - fsl,imx95-pcie
109    then:
110      properties:
111        reg:
112          minItems: 4
113          maxItems: 4
114        reg-names:
115          items:
116            - const: dbi
117            - const: config
118            - const: atu
119            - const: app
120
121  - if:
122      properties:
123        compatible:
124          enum:
125            - fsl,imx6sx-pcie
126    then:
127      properties:
128        clocks:
129          minItems: 4
130        clock-names:
131          items:
132            - const: pcie
133            - const: pcie_bus
134            - const: pcie_phy
135            - const: pcie_inbound_axi
136
137  - if:
138      properties:
139        compatible:
140          enum:
141            - fsl,imx8mq-pcie
142            - fsl,imx95-pcie
143    then:
144      properties:
145        clocks:
146          minItems: 4
147        clock-names:
148          items:
149            - const: pcie
150            - const: pcie_bus
151            - const: pcie_phy
152            - const: pcie_aux
153
154  - if:
155      properties:
156        compatible:
157          enum:
158            - fsl,imx6q-pcie
159            - fsl,imx6qp-pcie
160            - fsl,imx7d-pcie
161    then:
162      properties:
163        clocks:
164          maxItems: 3
165        clock-names:
166          items:
167            - const: pcie
168            - const: pcie_bus
169            - const: pcie_phy
170
171  - if:
172      properties:
173        compatible:
174          enum:
175            - fsl,imx8mm-pcie
176            - fsl,imx8mp-pcie
177    then:
178      properties:
179        clocks:
180          maxItems: 3
181        clock-names:
182          items:
183            - const: pcie
184            - const: pcie_bus
185            - const: pcie_aux
186
187unevaluatedProperties: false
188
189examples:
190  - |
191    #include <dt-bindings/clock/imx6qdl-clock.h>
192    #include <dt-bindings/interrupt-controller/arm-gic.h>
193
194    pcie: pcie@1ffc000 {
195        compatible = "fsl,imx6q-pcie";
196        reg = <0x01ffc000 0x04000>,
197              <0x01f00000 0x80000>;
198        reg-names = "dbi", "config";
199        #address-cells = <3>;
200        #size-cells = <2>;
201        device_type = "pci";
202        bus-range = <0x00 0xff>;
203        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
204                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
205        num-lanes = <1>;
206        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
207        interrupt-names = "msi";
208        #interrupt-cells = <1>;
209        interrupt-map-mask = <0 0 0 0x7>;
210        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
211                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
212                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
213                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
214        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
215                <&clks IMX6QDL_CLK_LVDS1_GATE>,
216                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
217        clock-names = "pcie", "pcie_bus", "pcie_phy";
218    };
219...
220