xref: /linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml (revision 50282fd57bcd3525c9d81eef58df8718e4337c6d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16  The controller instances are dual mode where in they can work either in
17  Root Port mode or Endpoint mode but one at a time.
18
19  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20  bindings.
21
22properties:
23  compatible:
24    enum:
25      - fsl,imx6q-pcie
26      - fsl,imx6sx-pcie
27      - fsl,imx6qp-pcie
28      - fsl,imx7d-pcie
29      - fsl,imx8mq-pcie
30      - fsl,imx8mm-pcie
31      - fsl,imx8mp-pcie
32
33  reg:
34    items:
35      - description: Data Bus Interface (DBI) registers.
36      - description: PCIe configuration space region.
37
38  reg-names:
39    items:
40      - const: dbi
41      - const: config
42
43  interrupts:
44    items:
45      - description: builtin MSI controller.
46
47  interrupt-names:
48    items:
49      - const: msi
50
51  reset-gpio:
52    description: Should specify the GPIO for controlling the PCI bus device
53      reset signal. It's not polarity aware and defaults to active-low reset
54      sequence (L=reset state, H=operation state) (optional required).
55
56  reset-gpio-active-high:
57    description: If present then the reset sequence using the GPIO
58      specified in the "reset-gpio" property is reversed (H=reset state,
59      L=operation state) (optional required).
60    type: boolean
61
62required:
63  - compatible
64  - reg
65  - reg-names
66  - "#address-cells"
67  - "#size-cells"
68  - device_type
69  - bus-range
70  - ranges
71  - interrupts
72  - interrupt-names
73  - "#interrupt-cells"
74  - interrupt-map-mask
75  - interrupt-map
76
77allOf:
78  - $ref: /schemas/pci/snps,dw-pcie.yaml#
79  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
80
81unevaluatedProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/imx6qdl-clock.h>
86    #include <dt-bindings/interrupt-controller/arm-gic.h>
87
88    pcie: pcie@1ffc000 {
89        compatible = "fsl,imx6q-pcie";
90        reg = <0x01ffc000 0x04000>,
91              <0x01f00000 0x80000>;
92        reg-names = "dbi", "config";
93        #address-cells = <3>;
94        #size-cells = <2>;
95        device_type = "pci";
96        bus-range = <0x00 0xff>;
97        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
98                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
99        num-lanes = <1>;
100        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
101        interrupt-names = "msi";
102        #interrupt-cells = <1>;
103        interrupt-map-mask = <0 0 0 0x7>;
104        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
105                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
106                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
107                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
108        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
109                <&clks IMX6QDL_CLK_LVDS1_GATE>,
110                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
111        clock-names = "pcie", "pcie_bus", "pcie_phy";
112    };
113...
114