1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX6 PCIe host controller 8 9maintainers: 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 12 13description: |+ 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 16 17allOf: 18 - $ref: /schemas/pci/snps,dw-pcie.yaml# 19 20properties: 21 compatible: 22 enum: 23 - fsl,imx6q-pcie 24 - fsl,imx6sx-pcie 25 - fsl,imx6qp-pcie 26 - fsl,imx7d-pcie 27 - fsl,imx8mq-pcie 28 - fsl,imx8mm-pcie 29 - fsl,imx8mp-pcie 30 31 reg: 32 items: 33 - description: Data Bus Interface (DBI) registers. 34 - description: PCIe configuration space region. 35 36 reg-names: 37 items: 38 - const: dbi 39 - const: config 40 41 interrupts: 42 items: 43 - description: builtin MSI controller. 44 45 interrupt-names: 46 items: 47 - const: msi 48 49 clocks: 50 minItems: 3 51 items: 52 - description: PCIe bridge clock. 53 - description: PCIe bus clock. 54 - description: PCIe PHY clock. 55 - description: Additional required clock entry for imx6sx-pcie, 56 imx8mq-pcie. 57 58 clock-names: 59 minItems: 3 60 items: 61 - const: pcie 62 - const: pcie_bus 63 - const: pcie_phy 64 - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie 65 66 num-lanes: 67 const: 1 68 69 fsl,imx7d-pcie-phy: 70 $ref: /schemas/types.yaml#/definitions/phandle 71 description: A phandle to an fsl,imx7d-pcie-phy node. Additional 72 required properties for imx7d-pcie and imx8mq-pcie. 73 74 power-domains: 75 items: 76 - description: The phandle pointing to the DISPLAY domain for 77 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and 78 imx8mq-pcie. 79 - description: The phandle pointing to the PCIE_PHY power domains 80 for imx6sx-pcie. 81 82 power-domain-names: 83 items: 84 - const: pcie 85 - const: pcie_phy 86 87 resets: 88 maxItems: 3 89 description: Phandles to PCIe-related reset lines exposed by SRC 90 IP block. Additional required by imx7d-pcie and imx8mq-pcie. 91 92 reset-names: 93 items: 94 - const: pciephy 95 - const: apps 96 - const: turnoff 97 98 fsl,tx-deemph-gen1: 99 description: Gen1 De-emphasis value (optional required). 100 $ref: /schemas/types.yaml#/definitions/uint32 101 default: 0 102 103 fsl,tx-deemph-gen2-3p5db: 104 description: Gen2 (3.5db) De-emphasis value (optional required). 105 $ref: /schemas/types.yaml#/definitions/uint32 106 default: 0 107 108 fsl,tx-deemph-gen2-6db: 109 description: Gen2 (6db) De-emphasis value (optional required). 110 $ref: /schemas/types.yaml#/definitions/uint32 111 default: 20 112 113 fsl,tx-swing-full: 114 description: Gen2 TX SWING FULL value (optional required). 115 $ref: /schemas/types.yaml#/definitions/uint32 116 default: 127 117 118 fsl,tx-swing-low: 119 description: TX launch amplitude swing_low value (optional required). 120 $ref: /schemas/types.yaml#/definitions/uint32 121 default: 127 122 123 fsl,max-link-speed: 124 description: Specify PCI Gen for link capability (optional required). 125 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter 126 requirements and thus for gen2 capability a gen2 compliant clock 127 generator should be used and configured. 128 $ref: /schemas/types.yaml#/definitions/uint32 129 enum: [1, 2, 3, 4] 130 default: 1 131 132 phys: 133 maxItems: 1 134 135 phy-names: 136 const: pcie-phy 137 138 reset-gpio: 139 description: Should specify the GPIO for controlling the PCI bus device 140 reset signal. It's not polarity aware and defaults to active-low reset 141 sequence (L=reset state, H=operation state) (optional required). 142 143 reset-gpio-active-high: 144 description: If present then the reset sequence using the GPIO 145 specified in the "reset-gpio" property is reversed (H=reset state, 146 L=operation state) (optional required). 147 type: boolean 148 149 vpcie-supply: 150 description: Should specify the regulator in charge of PCIe port power. 151 The regulator will be enabled when initializing the PCIe host and 152 disabled either as part of the init process or when shutting down 153 the host (optional required). 154 155 vph-supply: 156 description: Should specify the regulator in charge of VPH one of 157 the three PCIe PHY powers. This regulator can be supplied by both 158 1.8v and 3.3v voltage supplies (optional required). 159 160required: 161 - compatible 162 - reg 163 - reg-names 164 - "#address-cells" 165 - "#size-cells" 166 - device_type 167 - bus-range 168 - ranges 169 - num-lanes 170 - interrupts 171 - interrupt-names 172 - "#interrupt-cells" 173 - interrupt-map-mask 174 - interrupt-map 175 - clocks 176 - clock-names 177 178unevaluatedProperties: false 179 180examples: 181 - | 182 #include <dt-bindings/clock/imx6qdl-clock.h> 183 #include <dt-bindings/interrupt-controller/arm-gic.h> 184 185 pcie: pcie@1ffc000 { 186 compatible = "fsl,imx6q-pcie"; 187 reg = <0x01ffc000 0x04000>, 188 <0x01f00000 0x80000>; 189 reg-names = "dbi", "config"; 190 #address-cells = <3>; 191 #size-cells = <2>; 192 device_type = "pci"; 193 bus-range = <0x00 0xff>; 194 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, 195 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; 196 num-lanes = <1>; 197 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "msi"; 199 #interrupt-cells = <1>; 200 interrupt-map-mask = <0 0 0 0x7>; 201 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 202 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 203 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 204 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 206 <&clks IMX6QDL_CLK_LVDS1_GATE>, 207 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 208 clock-names = "pcie", "pcie_bus", "pcie_phy"; 209 }; 210... 211