xref: /linux/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml (revision 2948ce70e636d3803a17baa25d5e7d1e8ec844ae) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17allOf:
18  - $ref: /schemas/pci/snps,dw-pcie.yaml#
19
20properties:
21  compatible:
22    enum:
23      - fsl,imx6q-pcie
24      - fsl,imx6sx-pcie
25      - fsl,imx6qp-pcie
26      - fsl,imx7d-pcie
27      - fsl,imx8mq-pcie
28
29  reg:
30    items:
31      - description: Data Bus Interface (DBI) registers.
32      - description: PCIe configuration space region.
33
34  reg-names:
35    items:
36      - const: dbi
37      - const: config
38
39  interrupts:
40    items:
41      - description: builtin MSI controller.
42
43  interrupt-names:
44    items:
45      - const: msi
46
47  clocks:
48    minItems: 3
49    items:
50      - description: PCIe bridge clock.
51      - description: PCIe bus clock.
52      - description: PCIe PHY clock.
53      - description: Additional required clock entry for imx6sx-pcie,
54          imx8mq-pcie.
55
56  clock-names:
57    minItems: 3
58    items:
59      - const: pcie
60      - const: pcie_bus
61      - const: pcie_phy
62      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
63
64  num-lanes:
65    const: 1
66
67  fsl,imx7d-pcie-phy:
68    $ref: /schemas/types.yaml#/definitions/phandle
69    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
70      required properties for imx7d-pcie and imx8mq-pcie.
71
72  power-domains:
73    items:
74      - description: The phandle pointing to the DISPLAY domain for
75          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
76          imx8mq-pcie.
77      - description: The phandle pointing to the PCIE_PHY power domains
78          for imx6sx-pcie.
79
80  power-domain-names:
81    items:
82      - const: pcie
83      - const: pcie_phy
84
85  resets:
86    maxItems: 3
87    description: Phandles to PCIe-related reset lines exposed by SRC
88      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
89
90  reset-names:
91    items:
92      - const: pciephy
93      - const: apps
94      - const: turnoff
95
96  fsl,tx-deemph-gen1:
97    description: Gen1 De-emphasis value (optional required).
98    $ref: /schemas/types.yaml#/definitions/uint32
99    default: 0
100
101  fsl,tx-deemph-gen2-3p5db:
102    description: Gen2 (3.5db) De-emphasis value (optional required).
103    $ref: /schemas/types.yaml#/definitions/uint32
104    default: 0
105
106  fsl,tx-deemph-gen2-6db:
107    description: Gen2 (6db) De-emphasis value (optional required).
108    $ref: /schemas/types.yaml#/definitions/uint32
109    default: 20
110
111  fsl,tx-swing-full:
112    description: Gen2 TX SWING FULL value (optional required).
113    $ref: /schemas/types.yaml#/definitions/uint32
114    default: 127
115
116  fsl,tx-swing-low:
117    description: TX launch amplitude swing_low value (optional required).
118    $ref: /schemas/types.yaml#/definitions/uint32
119    default: 127
120
121  fsl,max-link-speed:
122    description: Specify PCI Gen for link capability (optional required).
123      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
124      requirements and thus for gen2 capability a gen2 compliant clock
125      generator should be used and configured.
126    $ref: /schemas/types.yaml#/definitions/uint32
127    enum: [1, 2, 3, 4]
128    default: 1
129
130  phys:
131    maxItems: 1
132
133  phy-names:
134    const: pcie-phy
135
136  reset-gpio:
137    description: Should specify the GPIO for controlling the PCI bus device
138      reset signal. It's not polarity aware and defaults to active-low reset
139      sequence (L=reset state, H=operation state) (optional required).
140
141  reset-gpio-active-high:
142    description: If present then the reset sequence using the GPIO
143      specified in the "reset-gpio" property is reversed (H=reset state,
144      L=operation state) (optional required).
145
146  vpcie-supply:
147    description: Should specify the regulator in charge of PCIe port power.
148      The regulator will be enabled when initializing the PCIe host and
149      disabled either as part of the init process or when shutting down
150      the host (optional required).
151
152  vph-supply:
153    description: Should specify the regulator in charge of VPH one of
154      the three PCIe PHY powers. This regulator can be supplied by both
155      1.8v and 3.3v voltage supplies (optional required).
156
157required:
158  - compatible
159  - reg
160  - reg-names
161  - "#address-cells"
162  - "#size-cells"
163  - device_type
164  - bus-range
165  - ranges
166  - num-lanes
167  - interrupts
168  - interrupt-names
169  - "#interrupt-cells"
170  - interrupt-map-mask
171  - interrupt-map
172  - clocks
173  - clock-names
174
175unevaluatedProperties: false
176
177examples:
178  - |
179    #include <dt-bindings/clock/imx6qdl-clock.h>
180    #include <dt-bindings/interrupt-controller/arm-gic.h>
181
182    pcie: pcie@1ffc000 {
183        compatible = "fsl,imx6q-pcie";
184        reg = <0x01ffc000 0x04000>,
185              <0x01f00000 0x80000>;
186        reg-names = "dbi", "config";
187        #address-cells = <3>;
188        #size-cells = <2>;
189        device_type = "pci";
190        bus-range = <0x00 0xff>;
191        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
192                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
193        num-lanes = <1>;
194        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
195        interrupt-names = "msi";
196        #interrupt-cells = <1>;
197        interrupt-map-mask = <0 0 0 0x7>;
198        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
199                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
200                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
201                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
202        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
203                <&clks IMX6QDL_CLK_LVDS1_GATE>,
204                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
205        clock-names = "pcie", "pcie_bus", "pcie_phy";
206    };
207...
208