1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Brcmstb PCIe Host Controller 8 9maintainers: 10 - Jim Quinlan <james.quinlan@broadcom.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - brcm,bcm2711-pcie # The Raspberry Pi 4 17 - brcm,bcm4908-pcie 18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4 19 - brcm,bcm7216-pcie # Broadcom 7216 Arm 20 - brcm,bcm7278-pcie # Broadcom 7278 Arm 21 - brcm,bcm7425-pcie # Broadcom 7425 MIPs 22 - brcm,bcm7435-pcie # Broadcom 7435 MIPs 23 - brcm,bcm7445-pcie # Broadcom 7445 Arm 24 - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 25 26 reg: 27 maxItems: 1 28 29 interrupts: 30 minItems: 1 31 items: 32 - description: PCIe host controller 33 - description: builtin MSI controller 34 35 interrupt-names: 36 minItems: 1 37 items: 38 - const: pcie 39 - const: msi 40 41 ranges: 42 minItems: 1 43 maxItems: 4 44 45 dma-ranges: 46 minItems: 1 47 maxItems: 6 48 49 clocks: 50 maxItems: 1 51 52 clock-names: 53 items: 54 - const: sw_pcie 55 56 msi-controller: 57 description: Identifies the node as an MSI controller. 58 59 msi-parent: 60 description: MSI controller the device is capable of using. 61 62 brcm,enable-ssc: 63 description: Indicates usage of spread-spectrum clocking. 64 type: boolean 65 66 aspm-no-l0s: true 67 68 brcm,clkreq-mode: 69 description: A string that determines the operating 70 clkreq mode of the PCIe RC HW with respect to controlling the refclk 71 signal. There are three different modes -- "safe", which drives the 72 refclk signal unconditionally and will work for all devices but does 73 not provide any power savings; "no-l1ss" -- which provides Clock 74 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) 75 power savings. If the downstream device connected to the RC is L1SS 76 capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, 77 potentially hanging the system; "default" -- which provides L0s, L1, 78 and L1SS, but not compliant to provide Clock Power Management; 79 specifically, may not be able to meet the T_CLRon max timing of 400ns 80 as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI 81 Express Mini CEM 2.1 specification. This situation is atypical and 82 should happen only with older devices. 83 $ref: /schemas/types.yaml#/definitions/string 84 enum: [ safe, no-l1ss, default ] 85 86 brcm,scb-sizes: 87 description: u64 giving the 64bit PCIe memory 88 viewport size of a memory controller. There may be up to 89 three controllers, and each size must be a power of two 90 with a size greater or equal to the amount of memory the 91 controller supports. Note that each memory controller 92 may have two component regions -- base and extended -- so 93 this information cannot be deduced from the dma-ranges. 94 $ref: /schemas/types.yaml#/definitions/uint64-array 95 minItems: 1 96 maxItems: 3 97 98 resets: 99 minItems: 1 100 maxItems: 3 101 102 reset-names: 103 minItems: 1 104 maxItems: 3 105 106required: 107 - compatible 108 - reg 109 - ranges 110 - dma-ranges 111 - "#interrupt-cells" 112 - interrupts 113 - interrupt-names 114 - interrupt-map-mask 115 - interrupt-map 116 - msi-controller 117 118allOf: 119 - $ref: /schemas/pci/pci-host-bridge.yaml# 120 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 121 - if: 122 properties: 123 compatible: 124 contains: 125 const: brcm,bcm4908-pcie 126 then: 127 properties: 128 resets: 129 maxItems: 1 130 131 reset-names: 132 items: 133 - const: perst 134 135 required: 136 - resets 137 - reset-names 138 - if: 139 properties: 140 compatible: 141 contains: 142 const: brcm,bcm7216-pcie 143 then: 144 properties: 145 resets: 146 maxItems: 1 147 148 reset-names: 149 items: 150 - const: rescal 151 152 required: 153 - resets 154 - reset-names 155 156 - if: 157 properties: 158 compatible: 159 contains: 160 const: brcm,bcm7712-pcie 161 then: 162 properties: 163 resets: 164 minItems: 3 165 maxItems: 3 166 167 reset-names: 168 items: 169 - const: rescal 170 - const: bridge 171 - const: swinit 172 173 required: 174 - resets 175 - reset-names 176 177unevaluatedProperties: false 178 179examples: 180 - | 181 #include <dt-bindings/interrupt-controller/irq.h> 182 #include <dt-bindings/interrupt-controller/arm-gic.h> 183 184 scb { 185 #address-cells = <2>; 186 #size-cells = <1>; 187 pcie0: pcie@7d500000 { 188 compatible = "brcm,bcm2711-pcie"; 189 reg = <0x0 0x7d500000 0x9310>; 190 device_type = "pci"; 191 #address-cells = <3>; 192 #size-cells = <2>; 193 #interrupt-cells = <1>; 194 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "pcie", "msi"; 197 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 198 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 199 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 200 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 201 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 202 203 msi-parent = <&pcie0>; 204 msi-controller; 205 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; 206 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, 207 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; 208 brcm,enable-ssc; 209 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; 210 211 /* PCIe bridge, Root Port */ 212 pci@0,0 { 213 #address-cells = <3>; 214 #size-cells = <2>; 215 reg = <0x0 0x0 0x0 0x0 0x0>; 216 compatible = "pciclass,0604"; 217 device_type = "pci"; 218 vpcie3v3-supply = <&vreg7>; 219 ranges; 220 221 /* PCIe endpoint */ 222 pci-ep@0,0 { 223 assigned-addresses = 224 <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; 225 reg = <0x0 0x0 0x0 0x0 0x0>; 226 compatible = "pci14e4,1688"; 227 }; 228 }; 229 }; 230 }; 231