1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Brcmstb PCIe Host Controller 8 9maintainers: 10 - Jim Quinlan <james.quinlan@broadcom.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - brcm,bcm2711-pcie # The Raspberry Pi 4 17 - brcm,bcm2712-pcie # Raspberry Pi 5 18 - brcm,bcm4908-pcie 19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4 20 - brcm,bcm7216-pcie # Broadcom 7216 Arm 21 - brcm,bcm7278-pcie # Broadcom 7278 Arm 22 - brcm,bcm7425-pcie # Broadcom 7425 MIPs 23 - brcm,bcm7435-pcie # Broadcom 7435 MIPs 24 - brcm,bcm7445-pcie # Broadcom 7445 Arm 25 - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 26 27 reg: 28 maxItems: 1 29 30 interrupts: 31 minItems: 1 32 items: 33 - description: PCIe host controller 34 - description: builtin MSI controller 35 36 interrupt-names: 37 minItems: 1 38 items: 39 - const: pcie 40 - const: msi 41 42 ranges: 43 minItems: 1 44 maxItems: 4 45 46 dma-ranges: 47 minItems: 1 48 maxItems: 6 49 50 clocks: 51 maxItems: 1 52 53 clock-names: 54 items: 55 - const: sw_pcie 56 57 msi-controller: 58 description: Identifies the node as an MSI controller. 59 60 msi-parent: 61 description: MSI controller the device is capable of using. 62 63 brcm,enable-ssc: 64 description: Indicates usage of spread-spectrum clocking. 65 type: boolean 66 67 aspm-no-l0s: true 68 69 brcm,clkreq-mode: 70 description: A string that determines the operating 71 clkreq mode of the PCIe RC HW with respect to controlling the refclk 72 signal. There are three different modes -- "safe", which drives the 73 refclk signal unconditionally and will work for all devices but does 74 not provide any power savings; "no-l1ss" -- which provides Clock 75 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) 76 power savings. If the downstream device connected to the RC is L1SS 77 capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, 78 potentially hanging the system; "default" -- which provides L0s, L1, 79 and L1SS, but not compliant to provide Clock Power Management; 80 specifically, may not be able to meet the T_CLRon max timing of 400ns 81 as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI 82 Express Mini CEM 2.1 specification. This situation is atypical and 83 should happen only with older devices. 84 $ref: /schemas/types.yaml#/definitions/string 85 enum: [ safe, no-l1ss, default ] 86 87 brcm,scb-sizes: 88 description: u64 giving the 64bit PCIe memory 89 viewport size of a memory controller. There may be up to 90 three controllers, and each size must be a power of two 91 with a size greater or equal to the amount of memory the 92 controller supports. Note that each memory controller 93 may have two component regions -- base and extended -- so 94 this information cannot be deduced from the dma-ranges. 95 $ref: /schemas/types.yaml#/definitions/uint64-array 96 minItems: 1 97 maxItems: 3 98 99 resets: 100 minItems: 1 101 maxItems: 3 102 103 reset-names: 104 minItems: 1 105 items: 106 - enum: [perst, rescal] 107 - const: bridge 108 - const: swinit 109 110 num-lanes: 111 default: 1 112 maximum: 4 113 114required: 115 - compatible 116 - reg 117 - ranges 118 - dma-ranges 119 - "#interrupt-cells" 120 - interrupts 121 - interrupt-names 122 - interrupt-map-mask 123 - interrupt-map 124 - msi-controller 125 126allOf: 127 - $ref: /schemas/pci/pci-host-bridge.yaml# 128 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 129 - if: 130 properties: 131 compatible: 132 contains: 133 const: brcm,bcm4908-pcie 134 then: 135 properties: 136 resets: 137 maxItems: 1 138 139 reset-names: 140 items: 141 - const: perst 142 143 required: 144 - resets 145 - reset-names 146 - if: 147 properties: 148 compatible: 149 contains: 150 const: brcm,bcm7216-pcie 151 then: 152 properties: 153 resets: 154 maxItems: 1 155 156 reset-names: 157 items: 158 - const: rescal 159 160 required: 161 - resets 162 - reset-names 163 164 - if: 165 properties: 166 compatible: 167 contains: 168 const: brcm,bcm7712-pcie 169 then: 170 properties: 171 resets: 172 minItems: 3 173 maxItems: 3 174 175 reset-names: 176 items: 177 - const: rescal 178 - const: bridge 179 - const: swinit 180 181 required: 182 - resets 183 - reset-names 184 185unevaluatedProperties: false 186 187examples: 188 - | 189 #include <dt-bindings/interrupt-controller/irq.h> 190 #include <dt-bindings/interrupt-controller/arm-gic.h> 191 192 scb { 193 #address-cells = <2>; 194 #size-cells = <1>; 195 pcie0: pcie@7d500000 { 196 compatible = "brcm,bcm2711-pcie"; 197 reg = <0x0 0x7d500000 0x9310>; 198 device_type = "pci"; 199 #address-cells = <3>; 200 #size-cells = <2>; 201 #interrupt-cells = <1>; 202 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-names = "pcie", "msi"; 205 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 206 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 207 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 208 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 209 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 210 211 msi-parent = <&pcie0>; 212 msi-controller; 213 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; 214 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, 215 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; 216 brcm,enable-ssc; 217 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; 218 219 /* PCIe bridge, Root Port */ 220 pci@0,0 { 221 #address-cells = <3>; 222 #size-cells = <2>; 223 reg = <0x0 0x0 0x0 0x0 0x0>; 224 compatible = "pciclass,0604"; 225 device_type = "pci"; 226 vpcie3v3-supply = <&vreg7>; 227 ranges; 228 229 /* PCIe endpoint */ 230 pci-ep@0,0 { 231 assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; 232 reg = <0x0 0x0 0x0 0x0 0x0>; 233 compatible = "pci14e4,1688"; 234 }; 235 }; 236 }; 237 }; 238