1*0956dcb8SJim Quinlan# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*0956dcb8SJim Quinlan%YAML 1.2 3*0956dcb8SJim Quinlan--- 4*0956dcb8SJim Quinlan$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# 5*0956dcb8SJim Quinlan$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0956dcb8SJim Quinlan 7*0956dcb8SJim Quinlantitle: Brcmstb PCIe Host Controller Device Tree Bindings 8*0956dcb8SJim Quinlan 9*0956dcb8SJim Quinlanmaintainers: 10*0956dcb8SJim Quinlan - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> 11*0956dcb8SJim Quinlan 12*0956dcb8SJim QuinlanallOf: 13*0956dcb8SJim Quinlan - $ref: /schemas/pci/pci-bus.yaml# 14*0956dcb8SJim Quinlan 15*0956dcb8SJim Quinlanproperties: 16*0956dcb8SJim Quinlan compatible: 17*0956dcb8SJim Quinlan const: brcm,bcm2711-pcie # The Raspberry Pi 4 18*0956dcb8SJim Quinlan 19*0956dcb8SJim Quinlan reg: 20*0956dcb8SJim Quinlan maxItems: 1 21*0956dcb8SJim Quinlan 22*0956dcb8SJim Quinlan interrupts: 23*0956dcb8SJim Quinlan minItems: 1 24*0956dcb8SJim Quinlan maxItems: 2 25*0956dcb8SJim Quinlan items: 26*0956dcb8SJim Quinlan - description: PCIe host controller 27*0956dcb8SJim Quinlan - description: builtin MSI controller 28*0956dcb8SJim Quinlan 29*0956dcb8SJim Quinlan interrupt-names: 30*0956dcb8SJim Quinlan minItems: 1 31*0956dcb8SJim Quinlan maxItems: 2 32*0956dcb8SJim Quinlan items: 33*0956dcb8SJim Quinlan - const: pcie 34*0956dcb8SJim Quinlan - const: msi 35*0956dcb8SJim Quinlan 36*0956dcb8SJim Quinlan ranges: 37*0956dcb8SJim Quinlan maxItems: 1 38*0956dcb8SJim Quinlan 39*0956dcb8SJim Quinlan dma-ranges: 40*0956dcb8SJim Quinlan maxItems: 1 41*0956dcb8SJim Quinlan 42*0956dcb8SJim Quinlan clocks: 43*0956dcb8SJim Quinlan maxItems: 1 44*0956dcb8SJim Quinlan 45*0956dcb8SJim Quinlan clock-names: 46*0956dcb8SJim Quinlan items: 47*0956dcb8SJim Quinlan - const: sw_pcie 48*0956dcb8SJim Quinlan 49*0956dcb8SJim Quinlan msi-controller: 50*0956dcb8SJim Quinlan description: Identifies the node as an MSI controller. 51*0956dcb8SJim Quinlan 52*0956dcb8SJim Quinlan msi-parent: 53*0956dcb8SJim Quinlan description: MSI controller the device is capable of using. 54*0956dcb8SJim Quinlan 55*0956dcb8SJim Quinlan brcm,enable-ssc: 56*0956dcb8SJim Quinlan description: Indicates usage of spread-spectrum clocking. 57*0956dcb8SJim Quinlan type: boolean 58*0956dcb8SJim Quinlan 59*0956dcb8SJim Quinlanrequired: 60*0956dcb8SJim Quinlan - reg 61*0956dcb8SJim Quinlan - dma-ranges 62*0956dcb8SJim Quinlan - "#interrupt-cells" 63*0956dcb8SJim Quinlan - interrupts 64*0956dcb8SJim Quinlan - interrupt-names 65*0956dcb8SJim Quinlan - interrupt-map-mask 66*0956dcb8SJim Quinlan - interrupt-map 67*0956dcb8SJim Quinlan - msi-controller 68*0956dcb8SJim Quinlan 69*0956dcb8SJim QuinlanunevaluatedProperties: false 70*0956dcb8SJim Quinlan 71*0956dcb8SJim Quinlanexamples: 72*0956dcb8SJim Quinlan - | 73*0956dcb8SJim Quinlan #include <dt-bindings/interrupt-controller/irq.h> 74*0956dcb8SJim Quinlan #include <dt-bindings/interrupt-controller/arm-gic.h> 75*0956dcb8SJim Quinlan 76*0956dcb8SJim Quinlan scb { 77*0956dcb8SJim Quinlan #address-cells = <2>; 78*0956dcb8SJim Quinlan #size-cells = <1>; 79*0956dcb8SJim Quinlan pcie0: pcie@7d500000 { 80*0956dcb8SJim Quinlan compatible = "brcm,bcm2711-pcie"; 81*0956dcb8SJim Quinlan reg = <0x0 0x7d500000 0x9310>; 82*0956dcb8SJim Quinlan device_type = "pci"; 83*0956dcb8SJim Quinlan #address-cells = <3>; 84*0956dcb8SJim Quinlan #size-cells = <2>; 85*0956dcb8SJim Quinlan #interrupt-cells = <1>; 86*0956dcb8SJim Quinlan interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 87*0956dcb8SJim Quinlan <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 88*0956dcb8SJim Quinlan interrupt-names = "pcie", "msi"; 89*0956dcb8SJim Quinlan interrupt-map-mask = <0x0 0x0 0x0 0x7>; 90*0956dcb8SJim Quinlan interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 91*0956dcb8SJim Quinlan msi-parent = <&pcie0>; 92*0956dcb8SJim Quinlan msi-controller; 93*0956dcb8SJim Quinlan ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; 94*0956dcb8SJim Quinlan dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; 95*0956dcb8SJim Quinlan brcm,enable-ssc; 96*0956dcb8SJim Quinlan }; 97*0956dcb8SJim Quinlan }; 98