1*3f3f67cbSNiklas Cassel* Axis ARTPEC-6 PCIe interface 2*3f3f67cbSNiklas Cassel 3*3f3f67cbSNiklas CasselThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 4*3f3f67cbSNiklas Casseland thus inherits all the common properties defined in designware-pcie.txt. 5*3f3f67cbSNiklas Cassel 6*3f3f67cbSNiklas CasselRequired properties: 7*3f3f67cbSNiklas Cassel- compatible: "axis,artpec6-pcie", "snps,dw-pcie" 8*3f3f67cbSNiklas Cassel- reg: base addresses and lengths of the PCIe controller (DBI), 9*3f3f67cbSNiklas Cassel the phy controller, and configuration address space. 10*3f3f67cbSNiklas Cassel- reg-names: Must include the following entries: 11*3f3f67cbSNiklas Cassel - "dbi" 12*3f3f67cbSNiklas Cassel - "phy" 13*3f3f67cbSNiklas Cassel - "config" 14*3f3f67cbSNiklas Cassel- interrupts: A list of interrupt outputs of the controller. Must contain an 15*3f3f67cbSNiklas Cassel entry for each entry in the interrupt-names property. 16*3f3f67cbSNiklas Cassel- interrupt-names: Must include the following entries: 17*3f3f67cbSNiklas Cassel - "msi": The interrupt that is asserted when an MSI is received 18*3f3f67cbSNiklas Cassel- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, 19*3f3f67cbSNiklas Cassel used to enable and control the Synopsys IP. 20*3f3f67cbSNiklas Cassel 21*3f3f67cbSNiklas CasselExample: 22*3f3f67cbSNiklas Cassel 23*3f3f67cbSNiklas Cassel pcie@f8050000 { 24*3f3f67cbSNiklas Cassel compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 25*3f3f67cbSNiklas Cassel reg = <0xf8050000 0x2000 26*3f3f67cbSNiklas Cassel 0xf8040000 0x1000 27*3f3f67cbSNiklas Cassel 0xc0000000 0x1000>; 28*3f3f67cbSNiklas Cassel reg-names = "dbi", "phy", "config"; 29*3f3f67cbSNiklas Cassel #address-cells = <3>; 30*3f3f67cbSNiklas Cassel #size-cells = <2>; 31*3f3f67cbSNiklas Cassel device_type = "pci"; 32*3f3f67cbSNiklas Cassel /* downstream I/O */ 33*3f3f67cbSNiklas Cassel ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000 34*3f3f67cbSNiklas Cassel /* non-prefetchable memory */ 35*3f3f67cbSNiklas Cassel 0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>; 36*3f3f67cbSNiklas Cassel num-lanes = <2>; 37*3f3f67cbSNiklas Cassel interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 38*3f3f67cbSNiklas Cassel interrupt-names = "msi"; 39*3f3f67cbSNiklas Cassel #interrupt-cells = <1>; 40*3f3f67cbSNiklas Cassel interrupt-map-mask = <0 0 0 0x7>; 41*3f3f67cbSNiklas Cassel interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 42*3f3f67cbSNiklas Cassel <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 43*3f3f67cbSNiklas Cassel <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 44*3f3f67cbSNiklas Cassel <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 45*3f3f67cbSNiklas Cassel axis,syscon-pcie = <&syscon>; 46*3f3f67cbSNiklas Cassel }; 47