1*bf9d32f2SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*bf9d32f2SRob Herring (Arm)%YAML 1.2 3*bf9d32f2SRob Herring (Arm)--- 4*bf9d32f2SRob Herring (Arm)$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml# 5*bf9d32f2SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*bf9d32f2SRob Herring (Arm) 7*bf9d32f2SRob Herring (Arm)title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge 8*bf9d32f2SRob Herring (Arm) 9*bf9d32f2SRob Herring (Arm)maintainers: 10*bf9d32f2SRob Herring (Arm) - Jonathan Chocron <jonnyc@amazon.com> 11*bf9d32f2SRob Herring (Arm) 12*bf9d32f2SRob Herring (Arm)description: 13*bf9d32f2SRob Herring (Arm) Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys 14*bf9d32f2SRob Herring (Arm) DesignWare PCI controller. 15*bf9d32f2SRob Herring (Arm) 16*bf9d32f2SRob Herring (Arm)allOf: 17*bf9d32f2SRob Herring (Arm) - $ref: snps,dw-pcie.yaml# 18*bf9d32f2SRob Herring (Arm) 19*bf9d32f2SRob Herring (Arm)properties: 20*bf9d32f2SRob Herring (Arm) compatible: 21*bf9d32f2SRob Herring (Arm) enum: 22*bf9d32f2SRob Herring (Arm) - amazon,al-alpine-v2-pcie 23*bf9d32f2SRob Herring (Arm) - amazon,al-alpine-v3-pcie 24*bf9d32f2SRob Herring (Arm) 25*bf9d32f2SRob Herring (Arm) reg: 26*bf9d32f2SRob Herring (Arm) items: 27*bf9d32f2SRob Herring (Arm) - description: PCIe ECAM space 28*bf9d32f2SRob Herring (Arm) - description: AL proprietary registers 29*bf9d32f2SRob Herring (Arm) - description: Designware PCIe registers 30*bf9d32f2SRob Herring (Arm) 31*bf9d32f2SRob Herring (Arm) reg-names: 32*bf9d32f2SRob Herring (Arm) items: 33*bf9d32f2SRob Herring (Arm) - const: config 34*bf9d32f2SRob Herring (Arm) - const: controller 35*bf9d32f2SRob Herring (Arm) - const: dbi 36*bf9d32f2SRob Herring (Arm) 37*bf9d32f2SRob Herring (Arm) interrupts: 38*bf9d32f2SRob Herring (Arm) maxItems: 1 39*bf9d32f2SRob Herring (Arm) 40*bf9d32f2SRob Herring (Arm)unevaluatedProperties: false 41*bf9d32f2SRob Herring (Arm) 42*bf9d32f2SRob Herring (Arm)required: 43*bf9d32f2SRob Herring (Arm) - compatible 44*bf9d32f2SRob Herring (Arm) - reg 45*bf9d32f2SRob Herring (Arm) - reg-names 46*bf9d32f2SRob Herring (Arm) 47*bf9d32f2SRob Herring (Arm)examples: 48*bf9d32f2SRob Herring (Arm) - | 49*bf9d32f2SRob Herring (Arm) #include <dt-bindings/interrupt-controller/arm-gic.h> 50*bf9d32f2SRob Herring (Arm) 51*bf9d32f2SRob Herring (Arm) bus { 52*bf9d32f2SRob Herring (Arm) #address-cells = <2>; 53*bf9d32f2SRob Herring (Arm) #size-cells = <2>; 54*bf9d32f2SRob Herring (Arm) 55*bf9d32f2SRob Herring (Arm) pcie@fb600000 { 56*bf9d32f2SRob Herring (Arm) compatible = "amazon,al-alpine-v3-pcie"; 57*bf9d32f2SRob Herring (Arm) reg = <0x0 0xfb600000 0x0 0x00100000 58*bf9d32f2SRob Herring (Arm) 0x0 0xfd800000 0x0 0x00010000 59*bf9d32f2SRob Herring (Arm) 0x0 0xfd810000 0x0 0x00001000>; 60*bf9d32f2SRob Herring (Arm) reg-names = "config", "controller", "dbi"; 61*bf9d32f2SRob Herring (Arm) bus-range = <0 255>; 62*bf9d32f2SRob Herring (Arm) device_type = "pci"; 63*bf9d32f2SRob Herring (Arm) #address-cells = <3>; 64*bf9d32f2SRob Herring (Arm) #size-cells = <2>; 65*bf9d32f2SRob Herring (Arm) #interrupt-cells = <1>; 66*bf9d32f2SRob Herring (Arm) interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 67*bf9d32f2SRob Herring (Arm) interrupt-map-mask = <0x00 0 0 7>; 68*bf9d32f2SRob Herring (Arm) interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */ 69*bf9d32f2SRob Herring (Arm) ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>; 70*bf9d32f2SRob Herring (Arm) }; 71*bf9d32f2SRob Herring (Arm) }; 72