xref: /linux/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2015, 2019, 2024, Intel Corporation
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Altera PCIe Root Port
9
10maintainers:
11  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
12
13properties:
14  compatible:
15    description: Each family of socfpga has its own implementation of the
16      PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
17      family of chips. The Stratix10 family of chips is supported by the
18      altr,pcie-root-port-2.0. The Agilex family of chips has three,
19      non-register compatible, variants of PCIe Hard IP referred to as the
20      F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
21
22    enum:
23      - altr,pcie-root-port-1.0
24      - altr,pcie-root-port-2.0
25      - altr,pcie-root-port-3.0-f-tile
26      - altr,pcie-root-port-3.0-p-tile
27      - altr,pcie-root-port-3.0-r-tile
28
29  reg:
30    items:
31      - description: TX slave port region
32      - description: Control register access region
33      - description: Hard IP region
34    minItems: 2
35
36  reg-names:
37    items:
38      - const: Txs
39      - const: Cra
40      - const: Hip
41    minItems: 2
42
43  interrupts:
44    maxItems: 1
45
46  interrupt-controller: true
47
48  interrupt-map-mask:
49    items:
50      - const: 0
51      - const: 0
52      - const: 0
53      - const: 7
54
55  interrupt-map:
56    maxItems: 4
57
58  "#interrupt-cells":
59    const: 1
60
61  msi-parent: true
62
63required:
64  - compatible
65  - reg
66  - reg-names
67  - interrupts
68  - "#interrupt-cells"
69  - interrupt-controller
70  - interrupt-map
71  - interrupt-map-mask
72
73allOf:
74  - $ref: /schemas/pci/pci-host-bridge.yaml#
75  - if:
76      properties:
77        compatible:
78          enum:
79            - altr,pcie-root-port-1.0
80    then:
81      properties:
82        reg:
83          maxItems: 2
84
85        reg-names:
86          maxItems: 2
87
88    else:
89      properties:
90        reg:
91          minItems: 3
92
93        reg-names:
94          minItems: 3
95
96
97unevaluatedProperties: false
98
99examples:
100  - |
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102    #include <dt-bindings/interrupt-controller/irq.h>
103    pcie_0: pcie@c00000000 {
104        compatible = "altr,pcie-root-port-1.0";
105        reg = <0xc0000000 0x20000000>,
106              <0xff220000 0x00004000>;
107        reg-names = "Txs", "Cra";
108        interrupt-parent = <&hps_0_arm_gic_0>;
109        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
110        interrupt-controller;
111        #interrupt-cells = <1>;
112        bus-range = <0x0 0xff>;
113        device_type = "pci";
114        msi-parent = <&msi_to_gic_gen_0>;
115        #address-cells = <3>;
116        #size-cells = <2>;
117        interrupt-map-mask = <0 0 0 7>;
118        interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,
119                        <0 0 0 2 &pcie_0 0 0 0 2>,
120                        <0 0 0 3 &pcie_0 0 0 0 3>,
121                        <0 0 0 4 &pcie_0 0 0 0 4>;
122        ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000>,
123                 <0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
124    };
125