1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. NVMEM OPP bindings 8 9maintainers: 10 - Ilia Lin <ilia.lin@kernel.org> 11 12allOf: 13 - $ref: opp-v2-base.yaml# 14 15description: | 16 In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996, 17 the CPU frequencies subset and voltage value of each OPP varies based on 18 the silicon variant in use. 19 Qualcomm Technologies, Inc. Process Voltage Scaling Tables 20 defines the voltage and frequency value based on the speedbin blown in 21 the efuse combination. 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). 24 This is used to determine the voltage and frequency value for each OPP of 25 operating-points-v2 table when it is parsed by the OPP framework. 26 27properties: 28 compatible: 29 const: operating-points-v2-kryo-cpu 30 31 nvmem-cells: 32 description: | 33 A phandle pointing to a nvmem-cells node representing the 34 efuse registers that has information about the 35 speedbin that is used to select the right frequency/voltage 36 value pair. 37 38 opp-shared: true 39 40patternProperties: 41 '^opp-?[0-9]+$': 42 type: object 43 44 properties: 45 opp-hz: true 46 47 opp-microvolt: true 48 49 opp-supported-hw: 50 description: | 51 A single 32 bit bitmap value, representing compatible HW. 52 Bitmap: 53 0: MSM8996, speedbin 0 54 1: MSM8996, speedbin 1 55 2: MSM8996, speedbin 2 56 3-31: unused 57 maximum: 0x7 58 59 clock-latency-ns: true 60 61 required-opps: true 62 63 required: 64 - opp-hz 65 66required: 67 - compatible 68 69if: 70 required: 71 - nvmem-cells 72then: 73 patternProperties: 74 '^opp-?[0-9]+$': 75 required: 76 - opp-supported-hw 77 78additionalProperties: false 79 80examples: 81 - | 82 / { 83 model = "Qualcomm Technologies, Inc. DB820c"; 84 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 88 cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo"; 95 reg = <0x0 0x0>; 96 enable-method = "psci"; 97 cpu-idle-states = <&CPU_SLEEP_0>; 98 capacity-dmips-mhz = <1024>; 99 clocks = <&kryocc 0>; 100 operating-points-v2 = <&cluster0_opp>; 101 power-domains = <&cpr>; 102 power-domain-names = "cpr"; 103 #cooling-cells = <2>; 104 next-level-cache = <&L2_0>; 105 L2_0: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 }; 109 }; 110 111 CPU1: cpu@1 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo"; 114 reg = <0x0 0x1>; 115 enable-method = "psci"; 116 cpu-idle-states = <&CPU_SLEEP_0>; 117 capacity-dmips-mhz = <1024>; 118 clocks = <&kryocc 0>; 119 operating-points-v2 = <&cluster0_opp>; 120 power-domains = <&cpr>; 121 power-domain-names = "cpr"; 122 #cooling-cells = <2>; 123 next-level-cache = <&L2_0>; 124 }; 125 126 CPU2: cpu@100 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo"; 129 reg = <0x0 0x100>; 130 enable-method = "psci"; 131 cpu-idle-states = <&CPU_SLEEP_0>; 132 capacity-dmips-mhz = <1024>; 133 clocks = <&kryocc 1>; 134 operating-points-v2 = <&cluster1_opp>; 135 power-domains = <&cpr>; 136 power-domain-names = "cpr"; 137 #cooling-cells = <2>; 138 next-level-cache = <&L2_1>; 139 L2_1: l2-cache { 140 compatible = "cache"; 141 cache-level = <2>; 142 }; 143 }; 144 145 CPU3: cpu@101 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo"; 148 reg = <0x0 0x101>; 149 enable-method = "psci"; 150 cpu-idle-states = <&CPU_SLEEP_0>; 151 capacity-dmips-mhz = <1024>; 152 clocks = <&kryocc 1>; 153 operating-points-v2 = <&cluster1_opp>; 154 power-domains = <&cpr>; 155 power-domain-names = "cpr"; 156 #cooling-cells = <2>; 157 next-level-cache = <&L2_1>; 158 }; 159 160 cpu-map { 161 cluster0 { 162 core0 { 163 cpu = <&CPU0>; 164 }; 165 166 core1 { 167 cpu = <&CPU1>; 168 }; 169 }; 170 171 cluster1 { 172 core0 { 173 cpu = <&CPU2>; 174 }; 175 176 core1 { 177 cpu = <&CPU3>; 178 }; 179 }; 180 }; 181 }; 182 183 cluster0_opp: opp-table-0 { 184 compatible = "operating-points-v2-kryo-cpu"; 185 nvmem-cells = <&speedbin_efuse>; 186 opp-shared; 187 188 opp-307200000 { 189 opp-hz = /bits/ 64 <307200000>; 190 opp-microvolt = <905000 905000 1140000>; 191 opp-supported-hw = <0x7>; 192 clock-latency-ns = <200000>; 193 required-opps = <&cpr_opp1>; 194 }; 195 opp-1401600000 { 196 opp-hz = /bits/ 64 <1401600000>; 197 opp-microvolt = <1140000 905000 1140000>; 198 opp-supported-hw = <0x5>; 199 clock-latency-ns = <200000>; 200 required-opps = <&cpr_opp2>; 201 }; 202 opp-1593600000 { 203 opp-hz = /bits/ 64 <1593600000>; 204 opp-microvolt = <1140000 905000 1140000>; 205 opp-supported-hw = <0x1>; 206 clock-latency-ns = <200000>; 207 required-opps = <&cpr_opp3>; 208 }; 209 }; 210 211 cluster1_opp: opp-table-1 { 212 compatible = "operating-points-v2-kryo-cpu"; 213 nvmem-cells = <&speedbin_efuse>; 214 opp-shared; 215 216 opp-307200000 { 217 opp-hz = /bits/ 64 <307200000>; 218 opp-microvolt = <905000 905000 1140000>; 219 opp-supported-hw = <0x7>; 220 clock-latency-ns = <200000>; 221 required-opps = <&cpr_opp1>; 222 }; 223 opp-1804800000 { 224 opp-hz = /bits/ 64 <1804800000>; 225 opp-microvolt = <1140000 905000 1140000>; 226 opp-supported-hw = <0x6>; 227 clock-latency-ns = <200000>; 228 required-opps = <&cpr_opp4>; 229 }; 230 opp-1900800000 { 231 opp-hz = /bits/ 64 <1900800000>; 232 opp-microvolt = <1140000 905000 1140000>; 233 opp-supported-hw = <0x4>; 234 clock-latency-ns = <200000>; 235 required-opps = <&cpr_opp5>; 236 }; 237 opp-2150400000 { 238 opp-hz = /bits/ 64 <2150400000>; 239 opp-microvolt = <1140000 905000 1140000>; 240 opp-supported-hw = <0x1>; 241 clock-latency-ns = <200000>; 242 required-opps = <&cpr_opp6>; 243 }; 244 }; 245 246 smem { 247 compatible = "qcom,smem"; 248 memory-region = <&smem_mem>; 249 hwlocks = <&tcsr_mutex 3>; 250 }; 251 252 soc { 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 qfprom: qfprom@74000 { 257 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 258 reg = <0x00074000 0x8ff>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 speedbin_efuse: speedbin@133 { 263 reg = <0x133 0x1>; 264 bits = <5 3>; 265 }; 266 }; 267 }; 268 }; 269