1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. NVMEM OPP 8 9maintainers: 10 - Ilia Lin <ilia.lin@kernel.org> 11 12allOf: 13 - $ref: opp-v2-base.yaml# 14 15description: | 16 In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996, 17 the CPU frequencies subset and voltage value of each OPP varies based on 18 the silicon variant in use. 19 Qualcomm Technologies, Inc. Process Voltage Scaling Tables 20 defines the voltage and frequency value based on the speedbin blown in 21 the efuse combination. 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). 24 This is used to determine the voltage and frequency value for each OPP of 25 operating-points-v2 table when it is parsed by the OPP framework. 26 27properties: 28 compatible: 29 enum: 30 - operating-points-v2-krait-cpu 31 - operating-points-v2-kryo-cpu 32 33 nvmem-cells: 34 description: | 35 A phandle pointing to a nvmem-cells node representing the 36 efuse registers that has information about the 37 speedbin that is used to select the right frequency/voltage 38 value pair. 39 40 opp-shared: true 41 42patternProperties: 43 '^opp-?[0-9]+$': 44 type: object 45 additionalProperties: false 46 47 properties: 48 opp-hz: true 49 50 opp-microvolt: true 51 52 opp-peak-kBps: true 53 54 opp-supported-hw: 55 description: | 56 A single 32 bit bitmap value, representing compatible HW. 57 Bitmap for MSM8996 format: 58 0: MSM8996, speedbin 0 59 1: MSM8996, speedbin 1 60 2: MSM8996, speedbin 2 61 3: MSM8996, speedbin 3 62 4-31: unused 63 64 Bitmap for MSM8996SG format (speedbin shifted of 4 left): 65 0-3: unused 66 4: MSM8996SG, speedbin 0 67 5: MSM8996SG, speedbin 1 68 6: MSM8996SG, speedbin 2 69 7-31: unused 70 71 Other platforms use bits directly corresponding to speedbin index. 72 73 clock-latency-ns: true 74 75 required-opps: true 76 77 patternProperties: 78 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true 79 80 required: 81 - opp-hz 82 83required: 84 - compatible 85 86if: 87 required: 88 - nvmem-cells 89then: 90 patternProperties: 91 '^opp-?[0-9]+$': 92 required: 93 - opp-supported-hw 94 95additionalProperties: false 96 97examples: 98 - | 99 / { 100 model = "Qualcomm Technologies, Inc. DB820c"; 101 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 105 cpus { 106 #address-cells = <2>; 107 #size-cells = <0>; 108 109 CPU0: cpu@0 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo"; 112 reg = <0x0 0x0>; 113 enable-method = "psci"; 114 cpu-idle-states = <&CPU_SLEEP_0>; 115 capacity-dmips-mhz = <1024>; 116 clocks = <&kryocc 0>; 117 operating-points-v2 = <&cluster0_opp>; 118 power-domains = <&cpr>; 119 power-domain-names = "cpr"; 120 #cooling-cells = <2>; 121 next-level-cache = <&L2_0>; 122 L2_0: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 }; 127 }; 128 129 CPU1: cpu@1 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo"; 132 reg = <0x0 0x1>; 133 enable-method = "psci"; 134 cpu-idle-states = <&CPU_SLEEP_0>; 135 capacity-dmips-mhz = <1024>; 136 clocks = <&kryocc 0>; 137 operating-points-v2 = <&cluster0_opp>; 138 power-domains = <&cpr>; 139 power-domain-names = "cpr"; 140 #cooling-cells = <2>; 141 next-level-cache = <&L2_0>; 142 }; 143 144 CPU2: cpu@100 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo"; 147 reg = <0x0 0x100>; 148 enable-method = "psci"; 149 cpu-idle-states = <&CPU_SLEEP_0>; 150 capacity-dmips-mhz = <1024>; 151 clocks = <&kryocc 1>; 152 operating-points-v2 = <&cluster1_opp>; 153 power-domains = <&cpr>; 154 power-domain-names = "cpr"; 155 #cooling-cells = <2>; 156 next-level-cache = <&L2_1>; 157 L2_1: l2-cache { 158 compatible = "cache"; 159 cache-level = <2>; 160 cache-unified; 161 }; 162 }; 163 164 CPU3: cpu@101 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo"; 167 reg = <0x0 0x101>; 168 enable-method = "psci"; 169 cpu-idle-states = <&CPU_SLEEP_0>; 170 capacity-dmips-mhz = <1024>; 171 clocks = <&kryocc 1>; 172 operating-points-v2 = <&cluster1_opp>; 173 power-domains = <&cpr>; 174 power-domain-names = "cpr"; 175 #cooling-cells = <2>; 176 next-level-cache = <&L2_1>; 177 }; 178 179 cpu-map { 180 cluster0 { 181 core0 { 182 cpu = <&CPU0>; 183 }; 184 185 core1 { 186 cpu = <&CPU1>; 187 }; 188 }; 189 190 cluster1 { 191 core0 { 192 cpu = <&CPU2>; 193 }; 194 195 core1 { 196 cpu = <&CPU3>; 197 }; 198 }; 199 }; 200 }; 201 202 cluster0_opp: opp-table-0 { 203 compatible = "operating-points-v2-kryo-cpu"; 204 nvmem-cells = <&speedbin_efuse>; 205 opp-shared; 206 207 opp-307200000 { 208 opp-hz = /bits/ 64 <307200000>; 209 opp-microvolt = <905000 905000 1140000>; 210 opp-supported-hw = <0x7>; 211 clock-latency-ns = <200000>; 212 required-opps = <&cpr_opp1>; 213 }; 214 opp-1401600000 { 215 opp-hz = /bits/ 64 <1401600000>; 216 opp-microvolt = <1140000 905000 1140000>; 217 opp-supported-hw = <0x5>; 218 clock-latency-ns = <200000>; 219 required-opps = <&cpr_opp2>; 220 }; 221 opp-1593600000 { 222 opp-hz = /bits/ 64 <1593600000>; 223 opp-microvolt = <1140000 905000 1140000>; 224 opp-supported-hw = <0x1>; 225 clock-latency-ns = <200000>; 226 required-opps = <&cpr_opp3>; 227 }; 228 }; 229 230 cluster1_opp: opp-table-1 { 231 compatible = "operating-points-v2-kryo-cpu"; 232 nvmem-cells = <&speedbin_efuse>; 233 opp-shared; 234 235 opp-307200000 { 236 opp-hz = /bits/ 64 <307200000>; 237 opp-microvolt = <905000 905000 1140000>; 238 opp-supported-hw = <0x7>; 239 clock-latency-ns = <200000>; 240 required-opps = <&cpr_opp1>; 241 }; 242 opp-1804800000 { 243 opp-hz = /bits/ 64 <1804800000>; 244 opp-microvolt = <1140000 905000 1140000>; 245 opp-supported-hw = <0x6>; 246 clock-latency-ns = <200000>; 247 required-opps = <&cpr_opp4>; 248 }; 249 opp-1900800000 { 250 opp-hz = /bits/ 64 <1900800000>; 251 opp-microvolt = <1140000 905000 1140000>; 252 opp-supported-hw = <0x4>; 253 clock-latency-ns = <200000>; 254 required-opps = <&cpr_opp5>; 255 }; 256 opp-2150400000 { 257 opp-hz = /bits/ 64 <2150400000>; 258 opp-microvolt = <1140000 905000 1140000>; 259 opp-supported-hw = <0x1>; 260 clock-latency-ns = <200000>; 261 required-opps = <&cpr_opp6>; 262 }; 263 }; 264 265 smem { 266 compatible = "qcom,smem"; 267 memory-region = <&smem_mem>; 268 hwlocks = <&tcsr_mutex 3>; 269 }; 270 271 soc { 272 #address-cells = <1>; 273 #size-cells = <1>; 274 275 qfprom: qfprom@74000 { 276 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 277 reg = <0x00074000 0x8ff>; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 281 speedbin_efuse: speedbin@133 { 282 reg = <0x133 0x1>; 283 bits = <5 3>; 284 }; 285 }; 286 }; 287 }; 288