1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner H6 CPU OPP 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: | 14 For some SoCs, the CPU frequency subset and voltage value of each 15 OPP varies based on the silicon variant in use. Allwinner Process 16 Voltage Scaling Tables define the voltage and frequency values based 17 on the speedbin blown in the efuse combination. 18 19allOf: 20 - $ref: opp-v2-base.yaml# 21 22properties: 23 compatible: 24 enum: 25 - allwinner,sun50i-h6-operating-points 26 - allwinner,sun50i-h616-operating-points 27 28 nvmem-cells: 29 description: | 30 A phandle pointing to a nvmem-cells node representing the efuse 31 register that has information about the speedbin that is used 32 to select the right frequency/voltage value pair. Please refer 33 to the nvmem-cells bindings in 34 Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the 35 examples below. 36 37 opp-shared: true 38 39required: 40 - compatible 41 - nvmem-cells 42 43patternProperties: 44 "^opp-[0-9]+$": 45 type: object 46 47 properties: 48 opp-hz: true 49 clock-latency-ns: true 50 opp-microvolt: true 51 opp-supported-hw: 52 maxItems: 1 53 description: 54 A single 32 bit bitmap value, representing compatible HW, one 55 bit per speed bin index. 56 57 patternProperties: 58 "^opp-microvolt-speed[0-9]$": true 59 60 required: 61 - opp-hz 62 63 unevaluatedProperties: false 64 65additionalProperties: false 66 67examples: 68 - | 69 cpu_opp_table: opp-table { 70 compatible = "allwinner,sun50i-h6-operating-points"; 71 nvmem-cells = <&speedbin_efuse>; 72 opp-shared; 73 74 opp-480000000 { 75 clock-latency-ns = <244144>; /* 8 32k periods */ 76 opp-hz = /bits/ 64 <480000000>; 77 78 opp-microvolt-speed0 = <880000>; 79 opp-microvolt-speed1 = <820000>; 80 opp-microvolt-speed2 = <800000>; 81 }; 82 83 opp-1080000000 { 84 clock-latency-ns = <244144>; /* 8 32k periods */ 85 opp-hz = /bits/ 64 <1080000000>; 86 87 opp-microvolt-speed0 = <1060000>; 88 opp-microvolt-speed1 = <880000>; 89 opp-microvolt-speed2 = <840000>; 90 }; 91 92 opp-1488000000 { 93 clock-latency-ns = <244144>; /* 8 32k periods */ 94 opp-hz = /bits/ 64 <1488000000>; 95 96 opp-microvolt-speed0 = <1160000>; 97 opp-microvolt-speed1 = <1000000>; 98 opp-microvolt-speed2 = <960000>; 99 }; 100 }; 101 102 - | 103 opp-table { 104 compatible = "allwinner,sun50i-h616-operating-points"; 105 nvmem-cells = <&speedbin_efuse>; 106 opp-shared; 107 108 opp-480000000 { 109 clock-latency-ns = <244144>; /* 8 32k periods */ 110 opp-hz = /bits/ 64 <480000000>; 111 112 opp-microvolt = <900000>; 113 opp-supported-hw = <0x1f>; 114 }; 115 116 opp-792000000 { 117 clock-latency-ns = <244144>; /* 8 32k periods */ 118 opp-hz = /bits/ 64 <792000000>; 119 120 opp-microvolt-speed1 = <900000>; 121 opp-microvolt-speed4 = <940000>; 122 opp-supported-hw = <0x12>; 123 }; 124 125 opp-1512000000 { 126 clock-latency-ns = <244144>; /* 8 32k periods */ 127 opp-hz = /bits/ 64 <1512000000>; 128 129 opp-microvolt = <1100000>; 130 opp-supported-hw = <0x0a>; 131 }; 132 }; 133 134... 135