xref: /linux/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml (revision 28f2aff1caa4997f58ca31179cad1b4a84a62827) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner H6 CPU OPP Device Tree Bindings
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13description: |
14  For some SoCs, the CPU frequency subset and voltage value of each
15  OPP varies based on the silicon variant in use. Allwinner Process
16  Voltage Scaling Tables defines the voltage and frequency value based
17  on the speedbin blown in the efuse combination. The
18  sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19  provide the OPP framework with required information.
20
21properties:
22  compatible:
23    const: allwinner,sun50i-h6-operating-points
24
25  nvmem-cells:
26    description: |
27      A phandle pointing to a nvmem-cells node representing the efuse
28      registers that has information about the speedbin that is used
29      to select the right frequency/voltage value pair. Please refer
30      the for nvmem-cells bindings
31      Documentation/devicetree/bindings/nvmem/nvmem.txt and also
32      examples below.
33
34required:
35  - compatible
36  - nvmem-cells
37
38patternProperties:
39  "opp-[0-9]+":
40    type: object
41
42    properties:
43      opp-hz: true
44
45    patternProperties:
46      "opp-microvolt-.*": true
47
48    required:
49      - opp-hz
50      - opp-microvolt-speed0
51      - opp-microvolt-speed1
52      - opp-microvolt-speed2
53
54    unevaluatedProperties: false
55
56unevaluatedProperties: false
57
58examples:
59  - |
60    cpu_opp_table: opp-table {
61        compatible = "allwinner,sun50i-h6-operating-points";
62        nvmem-cells = <&speedbin_efuse>;
63        opp-shared;
64
65        opp-480000000 {
66            clock-latency-ns = <244144>; /* 8 32k periods */
67            opp-hz = /bits/ 64 <480000000>;
68
69            opp-microvolt-speed0 = <880000>;
70            opp-microvolt-speed1 = <820000>;
71            opp-microvolt-speed2 = <800000>;
72        };
73
74        opp-720000000 {
75            clock-latency-ns = <244144>; /* 8 32k periods */
76            opp-hz = /bits/ 64 <720000000>;
77
78            opp-microvolt-speed0 = <880000>;
79            opp-microvolt-speed1 = <820000>;
80            opp-microvolt-speed2 = <800000>;
81        };
82
83        opp-816000000 {
84            clock-latency-ns = <244144>; /* 8 32k periods */
85            opp-hz = /bits/ 64 <816000000>;
86
87            opp-microvolt-speed0 = <880000>;
88            opp-microvolt-speed1 = <820000>;
89            opp-microvolt-speed2 = <800000>;
90        };
91
92        opp-888000000 {
93            clock-latency-ns = <244144>; /* 8 32k periods */
94            opp-hz = /bits/ 64 <888000000>;
95
96            opp-microvolt-speed0 = <940000>;
97            opp-microvolt-speed1 = <820000>;
98            opp-microvolt-speed2 = <800000>;
99        };
100
101        opp-1080000000 {
102            clock-latency-ns = <244144>; /* 8 32k periods */
103            opp-hz = /bits/ 64 <1080000000>;
104
105            opp-microvolt-speed0 = <1060000>;
106            opp-microvolt-speed1 = <880000>;
107            opp-microvolt-speed2 = <840000>;
108        };
109
110        opp-1320000000 {
111            clock-latency-ns = <244144>; /* 8 32k periods */
112            opp-hz = /bits/ 64 <1320000000>;
113
114            opp-microvolt-speed0 = <1160000>;
115            opp-microvolt-speed1 = <940000>;
116            opp-microvolt-speed2 = <900000>;
117        };
118
119        opp-1488000000 {
120            clock-latency-ns = <244144>; /* 8 32k periods */
121            opp-hz = /bits/ 64 <1488000000>;
122
123            opp-microvolt-speed0 = <1160000>;
124            opp-microvolt-speed1 = <1000000>;
125            opp-microvolt-speed2 = <960000>;
126        };
127    };
128
129...
130