1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip internal OTP (One Time Programmable) memory 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12properties: 13 compatible: 14 enum: 15 - rockchip,px30-otp 16 - rockchip,rk3308-otp 17 - rockchip,rk3576-otp 18 - rockchip,rk3588-otp 19 20 reg: 21 maxItems: 1 22 23 clocks: 24 minItems: 3 25 maxItems: 4 26 27 clock-names: 28 minItems: 3 29 items: 30 - const: otp 31 - const: apb_pclk 32 - const: phy 33 - const: arb 34 35 resets: 36 minItems: 1 37 maxItems: 3 38 39 reset-names: 40 minItems: 1 41 maxItems: 3 42 43required: 44 - compatible 45 - reg 46 - clocks 47 - clock-names 48 - resets 49 - reset-names 50 51allOf: 52 - $ref: nvmem.yaml# 53 - $ref: nvmem-deprecated-cells.yaml# 54 55 - if: 56 properties: 57 compatible: 58 contains: 59 enum: 60 - rockchip,px30-otp 61 - rockchip,rk3308-otp 62 then: 63 properties: 64 clocks: 65 maxItems: 3 66 clock-names: 67 maxItems: 3 68 resets: 69 maxItems: 1 70 reset-names: 71 items: 72 - const: phy 73 74 - if: 75 properties: 76 compatible: 77 contains: 78 enum: 79 - rockchip,rk3576-otp 80 then: 81 properties: 82 clocks: 83 maxItems: 3 84 clock-names: 85 maxItems: 3 86 resets: 87 minItems: 2 88 maxItems: 2 89 reset-names: 90 items: 91 - const: otp 92 - const: apb 93 94 - if: 95 properties: 96 compatible: 97 contains: 98 enum: 99 - rockchip,rk3588-otp 100 then: 101 properties: 102 clocks: 103 minItems: 4 104 clock-names: 105 minItems: 4 106 resets: 107 minItems: 3 108 reset-names: 109 items: 110 - const: otp 111 - const: apb 112 - const: arb 113 114unevaluatedProperties: false 115 116examples: 117 - | 118 #include <dt-bindings/clock/px30-cru.h> 119 120 soc { 121 #address-cells = <2>; 122 #size-cells = <2>; 123 124 otp: efuse@ff290000 { 125 compatible = "rockchip,px30-otp"; 126 reg = <0x0 0xff290000 0x0 0x4000>; 127 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 128 <&cru PCLK_OTP_PHY>; 129 clock-names = "otp", "apb_pclk", "phy"; 130 resets = <&cru SRST_OTP_PHY>; 131 reset-names = "phy"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 135 cpu_id: id@7 { 136 reg = <0x07 0x10>; 137 }; 138 139 cpu_leakage: cpu-leakage@17 { 140 reg = <0x17 0x1>; 141 }; 142 143 performance: performance@1e { 144 reg = <0x1e 0x1>; 145 bits = <4 3>; 146 }; 147 }; 148 }; 149