xref: /linux/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml (revision 34069d12e239ae8f36dd96c378e4622fb1c42a76) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip internal OTP (One Time Programmable) memory
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,px30-otp
16      - rockchip,rk3308-otp
17      - rockchip,rk3588-otp
18
19  reg:
20    maxItems: 1
21
22  clocks:
23    minItems: 3
24    maxItems: 4
25
26  clock-names:
27    minItems: 3
28    items:
29      - const: otp
30      - const: apb_pclk
31      - const: phy
32      - const: arb
33
34  resets:
35    minItems: 1
36    maxItems: 3
37
38  reset-names:
39    minItems: 1
40    maxItems: 3
41
42required:
43  - compatible
44  - reg
45  - clocks
46  - clock-names
47  - resets
48  - reset-names
49
50allOf:
51  - $ref: nvmem.yaml#
52
53  - if:
54      properties:
55        compatible:
56          contains:
57            enum:
58              - rockchip,px30-otp
59              - rockchip,rk3308-otp
60    then:
61      properties:
62        clocks:
63          maxItems: 3
64        resets:
65          maxItems: 1
66        reset-names:
67          items:
68            - const: phy
69
70  - if:
71      properties:
72        compatible:
73          contains:
74            enum:
75              - rockchip,rk3588-otp
76    then:
77      properties:
78        clocks:
79          minItems: 4
80        resets:
81          minItems: 3
82        reset-names:
83          items:
84            - const: otp
85            - const: apb
86            - const: arb
87
88unevaluatedProperties: false
89
90examples:
91  - |
92    #include <dt-bindings/clock/px30-cru.h>
93
94    soc {
95        #address-cells = <2>;
96        #size-cells = <2>;
97
98        otp: efuse@ff290000 {
99            compatible = "rockchip,px30-otp";
100            reg = <0x0 0xff290000 0x0 0x4000>;
101            clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
102                     <&cru PCLK_OTP_PHY>;
103            clock-names = "otp", "apb_pclk", "phy";
104            resets = <&cru SRST_OTP_PHY>;
105            reset-names = "phy";
106            #address-cells = <1>;
107            #size-cells = <1>;
108
109            cpu_id: id@7 {
110                reg = <0x07 0x10>;
111            };
112
113            cpu_leakage: cpu-leakage@17 {
114                reg = <0x17 0x1>;
115            };
116
117            performance: performance@1e {
118                reg = <0x1e 0x1>;
119                bits = <4 3>;
120            };
121        };
122    };
123