1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX On-Chip OTP Controller (OCOTP) 8 9maintainers: 10 - Anson Huang <Anson.Huang@nxp.com> 11 12description: | 13 This binding represents the on-chip eFuse OTP controller found on 14 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, 15 i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93 SoCs. 16 17allOf: 18 - $ref: nvmem.yaml# 19 20properties: 21 compatible: 22 oneOf: 23 - items: 24 - enum: 25 - fsl,imx6q-ocotp 26 - fsl,imx6sl-ocotp 27 - fsl,imx6sx-ocotp 28 - fsl,imx6ul-ocotp 29 - fsl,imx6ull-ocotp 30 - fsl,imx7d-ocotp 31 - fsl,imx6sll-ocotp 32 - fsl,imx7ulp-ocotp 33 - fsl,imx8mq-ocotp 34 - fsl,imx8mm-ocotp 35 - fsl,imx93-ocotp 36 - const: syscon 37 - items: 38 - enum: 39 - fsl,imx8mn-ocotp 40 # i.MX8MP not really compatible with fsl,imx8mm-ocotp, however 41 # the code for getting SoC revision depends on fsl,imx8mm-ocotp 42 # compatible. 43 - fsl,imx8mp-ocotp 44 - const: fsl,imx8mm-ocotp 45 - const: syscon 46 47 reg: 48 maxItems: 1 49 50 clocks: 51 maxItems: 1 52 53required: 54 - "#address-cells" 55 - "#size-cells" 56 - compatible 57 - reg 58 59unevaluatedProperties: false 60 61examples: 62 - | 63 #include <dt-bindings/clock/imx6sx-clock.h> 64 65 ocotp: efuse@21bc000 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "fsl,imx6sx-ocotp", "syscon"; 69 reg = <0x021bc000 0x4000>; 70 clocks = <&clks IMX6SX_CLK_OCOTP>; 71 72 cpu_speed_grade: speed-grade@10 { 73 reg = <0x10 4>; 74 }; 75 76 tempmon_calib: calib@38 { 77 reg = <0x38 4>; 78 }; 79 80 tempmon_temp_grade: temp-grade@20 { 81 reg = <0x20 4>; 82 }; 83 }; 84 85... 86