1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx GMII to RGMII Converter 8 9maintainers: 10 - Harini Katakam <harini.katakam@amd.com> 11 12description: 13 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media 14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant 15 ethernet physical media devices (PHY) and the Gigabit Ethernet controller. 16 This core can be used in all three modes of operation(10/100/1000 Mb/s). 17 The Management Data Input/Output (MDIO) interface is used to configure the 18 speed of operation. This core can switch dynamically between the three 19 different speed modes by configuring the converter register through mdio write. 20 The core cannot function without an external phy connected to it. 21 22properties: 23 compatible: 24 const: xlnx,gmii-to-rgmii-1.0 25 26 reg: 27 minimum: 0 28 maximum: 31 29 description: The ID number for the phy. 30 31 phy-handle: 32 $ref: ethernet-controller.yaml#/properties/phy-handle 33 34 clocks: 35 items: 36 - description: 200/375 MHz free-running clock is used as input clock. 37 38required: 39 - compatible 40 - reg 41 - phy-handle 42 43unevaluatedProperties: false 44 45examples: 46 - | 47 mdio { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 phy: ethernet-phy@0 { 52 reg = <0>; 53 }; 54 gmiitorgmii@8 { 55 compatible = "xlnx,gmii-to-rgmii-1.0"; 56 reg = <8>; 57 phy-handle = <&phy>; 58 clocks = <&dummy>; 59 }; 60 }; 61