1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: AXI 1G/2.5G Ethernet Subsystem 8 9description: | 10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 11 provides connectivity to an external ethernet PHY supporting different 12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two 13 segments of memory for buffering TX and RX, as well as the capability of 14 offloading TX/RX checksum calculation off the processor. 15 16 Management configuration is done through the AXI interface, while payload is 17 sent and received through means of an AXI DMA controller. This driver 18 includes the DMA driver code, so this driver is incompatible with AXI DMA 19 driver. 20 21maintainers: 22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> 23 24properties: 25 compatible: 26 enum: 27 - xlnx,axi-ethernet-1.00.a 28 - xlnx,axi-ethernet-1.01.a 29 - xlnx,axi-ethernet-2.01.a 30 31 reg: 32 description: 33 Address and length of the IO space, as well as the address 34 and length of the AXI DMA controller IO space, unless 35 axistream-connected is specified, in which case the reg 36 attribute of the node referenced by it is used. 37 minItems: 1 38 maxItems: 2 39 40 interrupts: 41 items: 42 - description: Ethernet core interrupt 43 - description: Tx DMA interrupt 44 - description: Rx DMA interrupt 45 description: 46 Ethernet core interrupt is optional. If axistream-connected property is 47 present DMA node should contains TX/RX DMA interrupts else DMA interrupt 48 resources are mentioned on ethernet node. 49 minItems: 1 50 51 phy-handle: true 52 53 xlnx,rxmem: 54 description: 55 Set to allocated memory buffer for Rx/Tx in the hardware. 56 $ref: /schemas/types.yaml#/definitions/uint32 57 58 phy-mode: 59 enum: 60 - mii 61 - gmii 62 - rgmii 63 - sgmii 64 - 1000BaseX 65 66 xlnx,phy-type: 67 description: 68 Do not use, but still accepted in preference to phy-mode. 69 deprecated: true 70 $ref: /schemas/types.yaml#/definitions/uint32 71 72 xlnx,txcsum: 73 description: 74 TX checksum offload. 0 or empty for disabling TX checksum offload, 75 1 to enable partial TX checksum offload and 2 to enable full TX 76 checksum offload. 77 $ref: /schemas/types.yaml#/definitions/uint32 78 enum: [0, 1, 2] 79 80 xlnx,rxcsum: 81 description: 82 RX checksum offload. 0 or empty for disabling RX checksum offload, 83 1 to enable partial RX checksum offload and 2 to enable full RX 84 checksum offload. 85 $ref: /schemas/types.yaml#/definitions/uint32 86 enum: [0, 1, 2] 87 88 xlnx,switch-x-sgmii: 89 type: boolean 90 description: 91 Indicate the Ethernet core is configured to support both 1000BaseX and 92 SGMII modes. If set, the phy-mode should be set to match the mode 93 selected on core reset (i.e. by the basex_or_sgmii core input line). 94 95 clocks: 96 items: 97 - description: Clock for AXI register slave interface. 98 - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces. 99 - description: Ethernet reference clock, used by signal delay primitives 100 and transceivers. 101 - description: MGT reference clock (used by optional internal PCS/PMA PHY) 102 103 clock-names: 104 items: 105 - const: s_axi_lite_clk 106 - const: axis_clk 107 - const: ref_clk 108 - const: mgt_clk 109 110 axistream-connected: 111 $ref: /schemas/types.yaml#/definitions/phandle 112 description: Phandle of AXI DMA controller which contains the resources 113 used by this device. If this is specified, the DMA-related resources 114 from that device (DMA registers and DMA TX/RX interrupts) rather than 115 this one will be used. 116 117 mdio: 118 type: object 119 120 pcs-handle: 121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X 122 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, 123 and "phy-handle" should point to an external PHY if exists. 124 maxItems: 1 125 126 dmas: 127 minItems: 2 128 maxItems: 32 129 description: TX and RX DMA channel phandle 130 131 dma-names: 132 items: 133 pattern: "^[tr]x_chan([0-9]|1[0-5])$" 134 description: 135 Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel 136 Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel 137 minItems: 2 138 maxItems: 32 139 140required: 141 - compatible 142 - interrupts 143 - reg 144 - xlnx,rxmem 145 - phy-handle 146 147allOf: 148 - $ref: /schemas/net/ethernet-controller.yaml# 149 150additionalProperties: false 151 152examples: 153 - | 154 axi_ethernet_eth: ethernet@40c00000 { 155 compatible = "xlnx,axi-ethernet-1.00.a"; 156 interrupts = <2 0 1>; 157 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; 158 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; 159 phy-mode = "mii"; 160 reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>; 161 dmas = <&xilinx_dma 0>, <&xilinx_dma 1>; 162 dma-names = "tx_chan0", "rx_chan0"; 163 xlnx,rxcsum = <0x2>; 164 xlnx,rxmem = <0x800>; 165 xlnx,txcsum = <0x2>; 166 phy-handle = <&phy0>; 167 168 mdio { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 phy0: ethernet-phy@1 { 172 device_type = "ethernet-phy"; 173 reg = <1>; 174 }; 175 }; 176 }; 177 178 - | 179 axi_ethernet_eth1: ethernet@40000000 { 180 compatible = "xlnx,axi-ethernet-1.00.a"; 181 interrupts = <0>; 182 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; 183 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; 184 phy-mode = "mii"; 185 reg = <0x40000000 0x40000>; 186 xlnx,rxcsum = <0x2>; 187 xlnx,rxmem = <0x800>; 188 xlnx,txcsum = <0x2>; 189 phy-handle = <&phy1>; 190 axistream-connected = <&dma>; 191 192 mdio { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 phy1: ethernet-phy@1 { 196 device_type = "ethernet-phy"; 197 reg = <1>; 198 }; 199 }; 200 }; 201