xref: /linux/Documentation/devicetree/bindings/net/xlnx,gmii-to-rgmii.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1c639a708SPranavi Somisetty# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2c639a708SPranavi Somisetty%YAML 1.2
3c639a708SPranavi Somisetty---
4c639a708SPranavi Somisetty$id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5c639a708SPranavi Somisetty$schema: http://devicetree.org/meta-schemas/core.yaml#
6c639a708SPranavi Somisetty
7c639a708SPranavi Somisettytitle: Xilinx GMII to RGMII Converter
8c639a708SPranavi Somisetty
9c639a708SPranavi Somisettymaintainers:
10c639a708SPranavi Somisetty  - Harini Katakam <harini.katakam@amd.com>
11c639a708SPranavi Somisetty
12c639a708SPranavi Somisettydescription:
13c639a708SPranavi Somisetty  The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
14c639a708SPranavi Somisetty  Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
15c639a708SPranavi Somisetty  ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
16c639a708SPranavi Somisetty  This core can be used in all three modes of operation(10/100/1000 Mb/s).
17c639a708SPranavi Somisetty  The Management Data Input/Output (MDIO) interface is used to configure the
18c639a708SPranavi Somisetty  speed of operation. This core can switch dynamically between the three
19c639a708SPranavi Somisetty  different speed modes by configuring the converter register through mdio write.
20c639a708SPranavi Somisetty  The core cannot function without an external phy connected to it.
21c639a708SPranavi Somisetty
22c639a708SPranavi Somisettyproperties:
23c639a708SPranavi Somisetty  compatible:
24c639a708SPranavi Somisetty    const: xlnx,gmii-to-rgmii-1.0
25c639a708SPranavi Somisetty
26c639a708SPranavi Somisetty  reg:
27c639a708SPranavi Somisetty    minimum: 0
28c639a708SPranavi Somisetty    maximum: 31
29c639a708SPranavi Somisetty    description: The ID number for the phy.
30c639a708SPranavi Somisetty
31c639a708SPranavi Somisetty  phy-handle:
32c639a708SPranavi Somisetty    $ref: ethernet-controller.yaml#/properties/phy-handle
33c639a708SPranavi Somisetty
34*c1d96671SVineeth Karumanchi  clocks:
35*c1d96671SVineeth Karumanchi    items:
36*c1d96671SVineeth Karumanchi      - description: 200/375 MHz free-running clock is used as input clock.
37*c1d96671SVineeth Karumanchi
38c639a708SPranavi Somisettyrequired:
39c639a708SPranavi Somisetty  - compatible
40c639a708SPranavi Somisetty  - reg
41c639a708SPranavi Somisetty  - phy-handle
42c639a708SPranavi Somisetty
43c639a708SPranavi SomisettyunevaluatedProperties: false
44c639a708SPranavi Somisetty
45c639a708SPranavi Somisettyexamples:
46c639a708SPranavi Somisetty  - |
47c639a708SPranavi Somisetty    mdio {
48c639a708SPranavi Somisetty        #address-cells = <1>;
49c639a708SPranavi Somisetty        #size-cells = <0>;
50c639a708SPranavi Somisetty
51c639a708SPranavi Somisetty        phy: ethernet-phy@0 {
52c639a708SPranavi Somisetty            reg = <0>;
53c639a708SPranavi Somisetty        };
54c639a708SPranavi Somisetty        gmiitorgmii@8 {
55c639a708SPranavi Somisetty            compatible = "xlnx,gmii-to-rgmii-1.0";
56c639a708SPranavi Somisetty            reg = <8>;
57c639a708SPranavi Somisetty            phy-handle = <&phy>;
58*c1d96671SVineeth Karumanchi            clocks = <&dummy>;
59c639a708SPranavi Somisetty        };
60c639a708SPranavi Somisetty    };
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