1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: AXI 1G/2.5G Ethernet Subsystem 8 9description: | 10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 11 provides connectivity to an external ethernet PHY supporting different 12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two 13 segments of memory for buffering TX and RX, as well as the capability of 14 offloading TX/RX checksum calculation off the processor. 15 16 Management configuration is done through the AXI interface, while payload is 17 sent and received through means of an AXI DMA controller. This driver 18 includes the DMA driver code, so this driver is incompatible with AXI DMA 19 driver. 20 21maintainers: 22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> 23 24properties: 25 compatible: 26 enum: 27 - xlnx,axi-ethernet-1.00.a 28 - xlnx,axi-ethernet-1.01.a 29 - xlnx,axi-ethernet-2.01.a 30 31 reg: 32 description: 33 Address and length of the IO space, as well as the address 34 and length of the AXI DMA controller IO space, unless 35 axistream-connected is specified, in which case the reg 36 attribute of the node referenced by it is used. 37 maxItems: 2 38 39 interrupts: 40 items: 41 - description: Ethernet core interrupt 42 - description: Tx DMA interrupt 43 - description: Rx DMA interrupt 44 description: 45 Ethernet core interrupt is optional. If axistream-connected property is 46 present DMA node should contains TX/RX DMA interrupts else DMA interrupt 47 resources are mentioned on ethernet node. 48 minItems: 1 49 50 phy-handle: true 51 52 xlnx,rxmem: 53 description: 54 Set to allocated memory buffer for Rx/Tx in the hardware. 55 $ref: /schemas/types.yaml#/definitions/uint32 56 57 phy-mode: 58 enum: 59 - mii 60 - gmii 61 - rgmii 62 - sgmii 63 - 1000BaseX 64 65 xlnx,phy-type: 66 description: 67 Do not use, but still accepted in preference to phy-mode. 68 deprecated: true 69 $ref: /schemas/types.yaml#/definitions/uint32 70 71 xlnx,txcsum: 72 description: 73 TX checksum offload. 0 or empty for disabling TX checksum offload, 74 1 to enable partial TX checksum offload and 2 to enable full TX 75 checksum offload. 76 $ref: /schemas/types.yaml#/definitions/uint32 77 enum: [0, 1, 2] 78 79 xlnx,rxcsum: 80 description: 81 RX checksum offload. 0 or empty for disabling RX checksum offload, 82 1 to enable partial RX checksum offload and 2 to enable full RX 83 checksum offload. 84 $ref: /schemas/types.yaml#/definitions/uint32 85 enum: [0, 1, 2] 86 87 xlnx,switch-x-sgmii: 88 type: boolean 89 description: 90 Indicate the Ethernet core is configured to support both 1000BaseX and 91 SGMII modes. If set, the phy-mode should be set to match the mode 92 selected on core reset (i.e. by the basex_or_sgmii core input line). 93 94 clocks: 95 items: 96 - description: Clock for AXI register slave interface. 97 - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces. 98 - description: Ethernet reference clock, used by signal delay primitives 99 and transceivers. 100 - description: MGT reference clock (used by optional internal PCS/PMA PHY) 101 102 clock-names: 103 items: 104 - const: s_axi_lite_clk 105 - const: axis_clk 106 - const: ref_clk 107 - const: mgt_clk 108 109 axistream-connected: 110 $ref: /schemas/types.yaml#/definitions/phandle 111 description: Phandle of AXI DMA controller which contains the resources 112 used by this device. If this is specified, the DMA-related resources 113 from that device (DMA registers and DMA TX/RX interrupts) rather than 114 this one will be used. 115 116 mdio: 117 type: object 118 119 pcs-handle: 120 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X 121 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, 122 and "phy-handle" should point to an external PHY if exists. 123 maxItems: 1 124 125 dmas: 126 minItems: 2 127 maxItems: 32 128 description: TX and RX DMA channel phandle 129 130 dma-names: 131 items: 132 pattern: "^[tr]x_chan([0-9]|1[0-5])$" 133 description: 134 Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel 135 Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel 136 minItems: 2 137 maxItems: 32 138 139required: 140 - compatible 141 - interrupts 142 - reg 143 - xlnx,rxmem 144 - phy-handle 145 146allOf: 147 - $ref: /schemas/net/ethernet-controller.yaml# 148 149additionalProperties: false 150 151examples: 152 - | 153 axi_ethernet_eth: ethernet@40c00000 { 154 compatible = "xlnx,axi-ethernet-1.00.a"; 155 interrupts = <2 0 1>; 156 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; 157 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; 158 phy-mode = "mii"; 159 reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>; 160 dmas = <&xilinx_dma 0>, <&xilinx_dma 1>; 161 dma-names = "tx_chan0", "rx_chan0"; 162 xlnx,rxcsum = <0x2>; 163 xlnx,rxmem = <0x800>; 164 xlnx,txcsum = <0x2>; 165 phy-handle = <&phy0>; 166 167 mdio { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 phy0: ethernet-phy@1 { 171 device_type = "ethernet-phy"; 172 reg = <1>; 173 }; 174 }; 175 }; 176 177 - | 178 axi_ethernet_eth1: ethernet@40000000 { 179 compatible = "xlnx,axi-ethernet-1.00.a"; 180 interrupts = <0>; 181 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; 182 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; 183 phy-mode = "mii"; 184 reg = <0x00 0x40000000 0x00 0x40000>; 185 xlnx,rxcsum = <0x2>; 186 xlnx,rxmem = <0x800>; 187 xlnx,txcsum = <0x2>; 188 phy-handle = <&phy1>; 189 axistream-connected = <&dma>; 190 191 mdio { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 phy1: ethernet-phy@1 { 195 device_type = "ethernet-phy"; 196 reg = <1>; 197 }; 198 }; 199 }; 200