1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments ICSSG PRUSS Ethernet 8 9maintainers: 10 - Md Danish Anwar <danishanwar@ti.com> 11 12description: 13 Ethernet based on the Programmable Real-Time Unit and Industrial 14 Communication Subsystem. 15 16properties: 17 compatible: 18 enum: 19 - ti,am642-icssg-prueth # for AM64x SoC family 20 - ti,am654-icssg-prueth # for AM65x SoC family 21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0 22 23 sram: 24 $ref: /schemas/types.yaml#/definitions/phandle 25 description: 26 phandle to MSMC SRAM node 27 28 dmas: 29 minItems: 10 30 maxItems: 12 31 32 dma-names: 33 minItems: 10 34 items: 35 - const: tx0-0 36 - const: tx0-1 37 - const: tx0-2 38 - const: tx0-3 39 - const: tx1-0 40 - const: tx1-1 41 - const: tx1-2 42 - const: tx1-3 43 - const: rx0 44 - const: rx1 45 - const: rxmgm0 46 - const: rxmgm1 47 48 ti,mii-g-rt: 49 $ref: /schemas/types.yaml#/definitions/phandle 50 description: 51 phandle to MII_G_RT module's syscon regmap. 52 53 ti,mii-rt: 54 $ref: /schemas/types.yaml#/definitions/phandle 55 description: 56 phandle to MII_RT module's syscon regmap 57 58 ti,iep: 59 $ref: /schemas/types.yaml#/definitions/phandle-array 60 maxItems: 2 61 items: 62 maxItems: 1 63 description: 64 phandle to IEP (Industrial Ethernet Peripheral) for ICSSG 65 66 interrupts: 67 maxItems: 2 68 description: 69 Interrupt specifiers to TX timestamp IRQ. 70 71 interrupt-names: 72 items: 73 - const: tx_ts0 74 - const: tx_ts1 75 76 ethernet-ports: 77 type: object 78 additionalProperties: false 79 80 properties: 81 '#address-cells': 82 const: 1 83 '#size-cells': 84 const: 0 85 86 patternProperties: 87 ^port@[0-1]$: 88 type: object 89 description: ICSSG PRUETH external ports 90 $ref: ethernet-controller.yaml# 91 unevaluatedProperties: false 92 93 properties: 94 reg: 95 items: 96 - enum: [0, 1] 97 description: ICSSG PRUETH port number 98 99 interrupts: 100 maxItems: 1 101 102 ti,syscon-rgmii-delay: 103 items: 104 - items: 105 - description: phandle to system controller node 106 - description: The offset to ICSSG control register 107 $ref: /schemas/types.yaml#/definitions/phandle-array 108 description: 109 phandle to system controller node and register offset 110 to ICSSG control register for RGMII transmit delay 111 112 ti,half-duplex-capable: 113 type: boolean 114 description: 115 Indicates that the PHY output pin COL is routed to ICSSG GPIO pin 116 (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is 117 capable of half duplex operations. 118 119 required: 120 - reg 121 anyOf: 122 - required: 123 - port@0 124 - required: 125 - port@1 126 127required: 128 - compatible 129 - sram 130 - dmas 131 - dma-names 132 - ethernet-ports 133 - ti,mii-g-rt 134 - interrupts 135 - interrupt-names 136 137allOf: 138 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml# 139 140 - if: 141 properties: 142 compatible: 143 contains: 144 const: ti,am654-sr1-icssg-prueth 145 then: 146 properties: 147 dmas: 148 minItems: 12 149 dma-names: 150 minItems: 12 151 else: 152 properties: 153 dmas: 154 maxItems: 10 155 dma-names: 156 maxItems: 10 157 158unevaluatedProperties: false 159 160examples: 161 - | 162 /* Example k3-am654 base board SR2.0, dual-emac */ 163 pruss2_eth: ethernet { 164 compatible = "ti,am654-icssg-prueth"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&icssg2_rgmii_pins_default>; 167 sram = <&msmc_ram>; 168 169 ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, 170 <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; 171 firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf", 172 "ti-pruss/am65x-rtu0-prueth-fw.elf", 173 "ti-pruss/am65x-txpru0-prueth-fw.elf", 174 "ti-pruss/am65x-pru1-prueth-fw.elf", 175 "ti-pruss/am65x-rtu1-prueth-fw.elf", 176 "ti-pruss/am65x-txpru1-prueth-fw.elf"; 177 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 178 <2>, 179 <2>, 180 <2>, /* MII mode */ 181 <2>, 182 <2>; 183 dmas = <&main_udmap 0xc300>, /* egress slice 0 */ 184 <&main_udmap 0xc301>, /* egress slice 0 */ 185 <&main_udmap 0xc302>, /* egress slice 0 */ 186 <&main_udmap 0xc303>, /* egress slice 0 */ 187 <&main_udmap 0xc304>, /* egress slice 1 */ 188 <&main_udmap 0xc305>, /* egress slice 1 */ 189 <&main_udmap 0xc306>, /* egress slice 1 */ 190 <&main_udmap 0xc307>, /* egress slice 1 */ 191 <&main_udmap 0x4300>, /* ingress slice 0 */ 192 <&main_udmap 0x4301>; /* ingress slice 1 */ 193 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 194 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 195 "rx0", "rx1"; 196 ti,mii-g-rt = <&icssg2_mii_g_rt>; 197 ti,iep = <&icssg2_iep0>, <&icssg2_iep1>; 198 interrupt-parent = <&icssg2_intc>; 199 interrupts = <24 0 2>, <25 1 3>; 200 interrupt-names = "tx_ts0", "tx_ts1"; 201 ethernet-ports { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 pruss2_emac0: port@0 { 205 reg = <0>; 206 phy-handle = <&pruss2_eth0_phy>; 207 phy-mode = "rgmii-id"; 208 interrupts-extended = <&icssg2_intc 24>; 209 ti,syscon-rgmii-delay = <&scm_conf 0x4120>; 210 /* Filled in by bootloader */ 211 local-mac-address = [00 00 00 00 00 00]; 212 }; 213 214 pruss2_emac1: port@1 { 215 reg = <1>; 216 phy-handle = <&pruss2_eth1_phy>; 217 phy-mode = "rgmii-id"; 218 interrupts-extended = <&icssg2_intc 25>; 219 ti,syscon-rgmii-delay = <&scm_conf 0x4124>; 220 /* Filled in by bootloader */ 221 local-mac-address = [00 00 00 00 00 00]; 222 }; 223 }; 224 }; 225