1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 2# Copyright (C) 2019 Texas Instruments Incorporated 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/net/ti,dp83867.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: TI DP83867 ethernet PHY 9 10allOf: 11 - $ref: ethernet-controller.yaml# 12 13maintainers: 14 - Andrew Davis <afd@ti.com> 15 16description: | 17 The DP83867 device is a robust, low power, fully featured Physical Layer 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 20 21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet 22 LANs. It interfaces directly to twisted pair media via an external 23 transformer. This device interfaces directly to the MAC layer through the 24 IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit 25 Media Independent Interface (GMII) or Reduced GMII (RGMII). 26 27 Specifications about the Ethernet PHY can be found at: 28 https://www.ti.com/lit/gpn/dp83867ir 29 30properties: 31 reg: 32 maxItems: 1 33 34 nvmem-cells: 35 maxItems: 1 36 description: 37 Nvmem data cell containing the value to write to the 38 IO_IMPEDANCE_CTRL field of the IO_MUX_CFG register. 39 40 nvmem-cell-names: 41 items: 42 - const: io_impedance_ctrl 43 44 ti,min-output-impedance: 45 type: boolean 46 description: | 47 MAC Interface Impedance control to set the programmable output impedance 48 to a minimum value (35 ohms). 49 50 ti,max-output-impedance: 51 type: boolean 52 description: | 53 MAC Interface Impedance control to set the programmable output impedance 54 to a maximum value (70 ohms). 55 Note: Specifying an io_impedance_ctrl nvmem cell or one of the 56 ti,min-output-impedance, ti,max-output-impedance properties 57 are mutually exclusive. If more than one is present, an nvmem 58 cell takes precedence over ti,max-output-impedance, which in 59 turn takes precedence over ti,min-output-impedance. 60 61 tx-fifo-depth: 62 $ref: /schemas/types.yaml#/definitions/uint32 63 description: | 64 Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values 65 66 rx-fifo-depth: 67 $ref: /schemas/types.yaml#/definitions/uint32 68 description: | 69 Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values 70 71 ti,clk-output-sel: 72 $ref: /schemas/types.yaml#/definitions/uint32 73 description: | 74 Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h 75 for applicable values. The CLK_OUT pin can also be disabled by this 76 property. When omitted, the PHY's default will be left as is. 77 78 ti,rx-internal-delay: 79 $ref: /schemas/types.yaml#/definitions/uint32 80 description: | 81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h 82 for applicable values. Required only if interface type is 83 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. 84 85 ti,tx-internal-delay: 86 $ref: /schemas/types.yaml#/definitions/uint32 87 description: | 88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 89 for applicable values. Required only if interface type is 90 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. 91 92 Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock 93 delays will be left at their default values, as set by the PHY's pin 94 strapping. The default strapping will use a delay of 2.00 ns. Thus 95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no 96 internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree 97 should use "rgmii-id" if internal delays are desired as this may be 98 changed in future to cause "rgmii" mode to disable delays. 99 100 ti,dp83867-rxctrl-strap-quirk: 101 type: boolean 102 description: | 103 This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in 104 mode 1 or 2. To ensure PHY operation, there are specific actions that 105 software needs to take when this pin is strapped in these modes. 106 See data manual for details. 107 108 ti,sgmii-ref-clock-output-enable: 109 type: boolean 110 description: | 111 This denotes which SGMII configuration is used (4 or 6-wire modes). 112 Some MACs work with differential SGMII clock. See data manual for details. 113 114 ti,fifo-depth: 115 deprecated: true 116 $ref: /schemas/types.yaml#/definitions/uint32 117 description: | 118 Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable 119 values. 120 121required: 122 - reg 123 124unevaluatedProperties: false 125 126examples: 127 - | 128 #include <dt-bindings/net/ti-dp83867.h> 129 mdio0 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 ethphy0: ethernet-phy@0 { 133 reg = <0>; 134 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 135 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 136 ti,max-output-impedance; 137 ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>; 138 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 139 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 140 }; 141 }; 142