xref: /linux/Documentation/devicetree/bindings/net/ti,dp83822.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/ti,dp83822.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI DP83822 ethernet PHY
9
10maintainers:
11  - Andrew Davis <afd@ti.com>
12
13description: |
14  The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
15  provides all of the physical layer functions needed to transmit and receive
16  data over standard, twisted-pair cables or to connect to an external,
17  fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
18  connect to a MAC through a standard MII, RMII, or RGMII interface
19
20  Specifications about the Ethernet PHY can be found at:
21    http://www.ti.com/lit/ds/symlink/dp83822i.pdf
22
23allOf:
24  - $ref: ethernet-phy.yaml#
25
26properties:
27  reg:
28    maxItems: 1
29
30  ti,link-loss-low:
31    type: boolean
32    description: |
33       DP83822 PHY in Fiber mode only.
34       Sets the DP83822 to detect a link drop condition when the signal goes
35       high.  If not set then link drop will occur when the signal goes low.
36       This property is only applicable if the fiber mode support is strapped
37       to on.
38
39  ti,fiber-mode:
40    type: boolean
41    description: |
42       DP83822 PHY only.
43       If present the DP83822 PHY is configured to operate in fiber mode
44       Fiber mode support can also be strapped. If the strap pin is not set
45       correctly or not set at all then this boolean can be used to enable it.
46       If the fiber mode is not strapped then signal detection for the PHY
47       is disabled.
48       In fiber mode, auto-negotiation is disabled and the PHY can only work in
49       100base-fx (full and half duplex) modes.
50       This property is deprecated, for details please refer to
51       Documentation/devicetree/bindings/net/ethernet-connector.yaml
52    deprecated: true
53
54  rx-internal-delay-ps:
55    description: |
56       DP83822 PHY only.
57       Setting this property to a non-zero number sets the RX internal delay
58       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
59       to receive data.
60
61  tx-internal-delay-ps:
62    description: |
63       DP83822 PHY only.
64       Setting this property to a non-zero number sets the TX internal delay
65       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
66       to transmit data.
67
68  ti,cfg-dac-minus-one-bp:
69    description: |
70       DP83826 PHY only.
71       Sets the voltage ratio (with respect to the nominal value)
72       of the logical level -1 for the MLT-3 encoded TX data.
73    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
74           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
75    default: 10000
76
77  ti,cfg-dac-plus-one-bp:
78    description: |
79       DP83826 PHY only.
80       Sets the voltage ratio (with respect to the nominal value)
81       of the logical level +1 for the MLT-3 encoded TX data.
82    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
83           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
84    default: 10000
85
86  ti,rmii-mode:
87    description: |
88       If present, select the RMII operation mode. Two modes are
89       available:
90         - RMII master, where the PHY outputs a 50MHz reference clock which can
91         be connected to the MAC.
92         - RMII slave, where the PHY expects a 50MHz reference clock input
93         shared with the MAC.
94       The RMII operation mode can also be configured by its straps.
95       If the strap pin is not set correctly or not set at all, then this can be
96       used to configure it.
97    $ref: /schemas/types.yaml#/definitions/string
98    enum:
99      - master
100      - slave
101
102  ti,gpio2-clk-out:
103    description: |
104       DP83822 PHY only.
105       The GPIO2 pin on the DP83822 can be configured as clock output. When
106       omitted, the PHY's default will be left as is.
107
108       - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
109         clock frequency is 50-MHz and in RGMII Mode the clock frequency is
110         25-MHz.
111       - 'xi': XI clock(pass-through clock from XI pin).
112       - 'int-ref': Internal reference clock 25-MHz.
113       - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
114         master mode reference clock is identical to MAC IF clock in RMII master
115         mode.
116       - 'free-running': Free running clock 125-MHz.
117       - 'recovered': Recovered clock is a 125-MHz recovered clock from a
118         connected link partner.
119    $ref: /schemas/types.yaml#/definitions/string
120    enum:
121      - mac-if
122      - xi
123      - int-ref
124      - rmii-master-mode-ref
125      - free-running
126      - recovered
127
128  mac-termination-ohms:
129    enum: [43, 44, 46, 48, 50, 53, 55, 58, 61, 65, 69, 73, 78, 84, 91, 99]
130
131required:
132  - reg
133
134unevaluatedProperties: false
135
136examples:
137  - |
138    mdio0 {
139      #address-cells = <1>;
140      #size-cells = <0>;
141      ethphy0: ethernet-phy@0 {
142        reg = <0>;
143        rx-internal-delay-ps = <1>;
144        tx-internal-delay-ps = <1>;
145        ti,gpio2-clk-out = "xi";
146        mac-termination-ohms = <43>;
147        mdi {
148          connector-0 {
149            media = "BaseF";
150          };
151        };
152      };
153    };
154...
155