1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI SoC Ethernet Switch Controller (CPSW) 8 9maintainers: 10 - Siddharth Vadapalli <s-vadapalli@ti.com> 11 - Ravi Gunasekaran <r-gunasekaran@ti.com> 12 - Roger Quadros <rogerq@kernel.org> 13 14description: 15 The 3-port switch gigabit ethernet subsystem provides ethernet packet 16 communication and can be configured as an ethernet switch. It provides the 17 gigabit media independent interface (GMII),reduced gigabit media 18 independent interface (RGMII), reduced media independent interface (RMII), 19 the management data input output (MDIO) for physical layer device (PHY) 20 management. 21 22properties: 23 compatible: 24 oneOf: 25 - const: ti,cpsw-switch 26 - items: 27 - const: ti,am335x-cpsw-switch 28 - const: ti,cpsw-switch 29 - items: 30 - const: ti,am4372-cpsw-switch 31 - const: ti,cpsw-switch 32 - items: 33 - const: ti,dra7-cpsw-switch 34 - const: ti,cpsw-switch 35 36 reg: 37 maxItems: 1 38 description: 39 The physical base address and size of full the CPSW module IO range 40 41 '#address-cells': 42 const: 1 43 44 '#size-cells': 45 const: 1 46 47 ranges: true 48 49 clocks: 50 maxItems: 1 51 description: CPSW functional clock 52 53 clock-names: 54 items: 55 - const: fck 56 57 interrupts: 58 items: 59 - description: RX_THRESH interrupt 60 - description: RX interrupt 61 - description: TX interrupt 62 - description: MISC interrupt 63 64 interrupt-names: 65 items: 66 - const: rx_thresh 67 - const: rx 68 - const: tx 69 - const: misc 70 71 pinctrl-names: true 72 73 syscon: 74 $ref: /schemas/types.yaml#/definitions/phandle 75 description: 76 Phandle to the system control device node which provides access to 77 efuse IO range with MAC addresses 78 79 ethernet-ports: 80 type: object 81 additionalProperties: false 82 83 properties: 84 '#address-cells': 85 const: 1 86 '#size-cells': 87 const: 0 88 89 patternProperties: 90 "^port@[12]$": 91 type: object 92 description: CPSW external ports 93 94 $ref: ethernet-controller.yaml# 95 unevaluatedProperties: false 96 97 properties: 98 reg: 99 items: 100 - enum: [1, 2] 101 description: CPSW port number 102 103 phys: 104 maxItems: 1 105 description: phandle on phy-gmii-sel PHY 106 107 label: 108 description: label associated with this port 109 110 ti,dual-emac-pvid: 111 $ref: /schemas/types.yaml#/definitions/uint32 112 minimum: 1 113 maximum: 1024 114 description: 115 Specifies default PORT VID to be used to segregate 116 ports. Default value - CPSW port number. 117 118 required: 119 - reg 120 - phys 121 122 cpts: 123 type: object 124 unevaluatedProperties: false 125 description: 126 The Common Platform Time Sync (CPTS) module 127 128 properties: 129 clocks: 130 maxItems: 1 131 description: CPTS reference clock 132 133 clock-names: 134 items: 135 - const: cpts 136 137 cpts_clock_mult: 138 $ref: /schemas/types.yaml#/definitions/uint32 139 description: 140 Numerator to convert input clock ticks into ns 141 142 cpts_clock_shift: 143 $ref: /schemas/types.yaml#/definitions/uint32 144 description: 145 Denominator to convert input clock ticks into ns. 146 Mult and shift will be calculated basing on CPTS rftclk frequency if 147 both cpts_clock_shift and cpts_clock_mult properties are not provided. 148 149 required: 150 - clocks 151 - clock-names 152 153patternProperties: 154 "^mdio@": 155 type: object 156 description: 157 CPSW MDIO bus. 158 $ref: ti,davinci-mdio.yaml# 159 160 161required: 162 - compatible 163 - reg 164 - ranges 165 - clocks 166 - clock-names 167 - interrupts 168 - interrupt-names 169 - '#address-cells' 170 - '#size-cells' 171 172additionalProperties: false 173 174examples: 175 - | 176 #include <dt-bindings/interrupt-controller/irq.h> 177 #include <dt-bindings/interrupt-controller/arm-gic.h> 178 #include <dt-bindings/clock/dra7.h> 179 180 mac_sw: switch@0 { 181 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; 182 reg = <0x0 0x4000>; 183 ranges = <0 0 0x4000>; 184 clocks = <&gmac_main_clk>; 185 clock-names = "fck"; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 syscon = <&scm_conf>; 189 190 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 195 196 ethernet-ports { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 cpsw_port1: port@1 { 201 reg = <1>; 202 label = "port1"; 203 mac-address = [ 00 00 00 00 00 00 ]; 204 phys = <&phy_gmii_sel 1>; 205 phy-handle = <ðphy0_sw>; 206 phy-mode = "rgmii"; 207 ti,dual-emac-pvid = <1>; 208 }; 209 210 cpsw_port2: port@2 { 211 reg = <2>; 212 label = "wan"; 213 mac-address = [ 00 00 00 00 00 00 ]; 214 phys = <&phy_gmii_sel 2>; 215 phy-handle = <ðphy1_sw>; 216 phy-mode = "rgmii"; 217 ti,dual-emac-pvid = <2>; 218 }; 219 }; 220 221 davinci_mdio_sw: mdio@1000 { 222 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 223 reg = <0x1000 0x100>; 224 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 225 clock-names = "fck"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 bus_freq = <1000000>; 229 230 ethphy0_sw: ethernet-phy@0 { 231 reg = <0>; 232 }; 233 234 ethphy1_sw: ethernet-phy@1 { 235 reg = <1>; 236 }; 237 }; 238 239 cpts { 240 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 241 clock-names = "cpts"; 242 }; 243 }; 244