1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI SoC Ethernet Switch Controller (CPSW) 8 9maintainers: 10 - Siddharth Vadapalli <s-vadapalli@ti.com> 11 - Roger Quadros <rogerq@kernel.org> 12 13description: 14 The 3-port switch gigabit ethernet subsystem provides ethernet packet 15 communication and can be configured as an ethernet switch. It provides the 16 gigabit media independent interface (GMII),reduced gigabit media 17 independent interface (RGMII), reduced media independent interface (RMII), 18 the management data input output (MDIO) for physical layer device (PHY) 19 management. 20 21properties: 22 compatible: 23 oneOf: 24 - const: ti,cpsw-switch 25 - items: 26 - const: ti,am335x-cpsw-switch 27 - const: ti,cpsw-switch 28 - items: 29 - const: ti,am4372-cpsw-switch 30 - const: ti,cpsw-switch 31 - items: 32 - const: ti,dra7-cpsw-switch 33 - const: ti,cpsw-switch 34 35 reg: 36 maxItems: 1 37 description: 38 The physical base address and size of full the CPSW module IO range 39 40 '#address-cells': 41 const: 1 42 43 '#size-cells': 44 const: 1 45 46 ranges: true 47 48 clocks: 49 maxItems: 1 50 description: CPSW functional clock 51 52 clock-names: 53 items: 54 - const: fck 55 56 interrupts: 57 items: 58 - description: RX_THRESH interrupt 59 - description: RX interrupt 60 - description: TX interrupt 61 - description: MISC interrupt 62 63 interrupt-names: 64 items: 65 - const: rx_thresh 66 - const: rx 67 - const: tx 68 - const: misc 69 70 pinctrl-names: true 71 72 syscon: 73 $ref: /schemas/types.yaml#/definitions/phandle 74 description: 75 Phandle to the system control device node which provides access to 76 efuse IO range with MAC addresses 77 78 ethernet-ports: 79 type: object 80 additionalProperties: false 81 82 properties: 83 '#address-cells': 84 const: 1 85 '#size-cells': 86 const: 0 87 88 patternProperties: 89 "^port@[12]$": 90 type: object 91 description: CPSW external ports 92 93 $ref: ethernet-controller.yaml# 94 unevaluatedProperties: false 95 96 properties: 97 reg: 98 items: 99 - enum: [1, 2] 100 description: CPSW port number 101 102 phys: 103 maxItems: 1 104 description: phandle on phy-gmii-sel PHY 105 106 label: 107 description: label associated with this port 108 109 ti,dual-emac-pvid: 110 $ref: /schemas/types.yaml#/definitions/uint32 111 minimum: 1 112 maximum: 1024 113 description: 114 Specifies default PORT VID to be used to segregate 115 ports. Default value - CPSW port number. 116 117 required: 118 - reg 119 - phys 120 121 cpts: 122 type: object 123 unevaluatedProperties: false 124 description: 125 The Common Platform Time Sync (CPTS) module 126 127 properties: 128 clocks: 129 maxItems: 1 130 description: CPTS reference clock 131 132 clock-names: 133 items: 134 - const: cpts 135 136 cpts_clock_mult: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 description: 139 Numerator to convert input clock ticks into ns 140 141 cpts_clock_shift: 142 $ref: /schemas/types.yaml#/definitions/uint32 143 description: 144 Denominator to convert input clock ticks into ns. 145 Mult and shift will be calculated basing on CPTS rftclk frequency if 146 both cpts_clock_shift and cpts_clock_mult properties are not provided. 147 148 required: 149 - clocks 150 - clock-names 151 152patternProperties: 153 "^mdio@": 154 type: object 155 description: 156 CPSW MDIO bus. 157 $ref: ti,davinci-mdio.yaml# 158 159required: 160 - compatible 161 - reg 162 - ranges 163 - clocks 164 - clock-names 165 - interrupts 166 - interrupt-names 167 - '#address-cells' 168 - '#size-cells' 169 170additionalProperties: false 171 172examples: 173 - | 174 #include <dt-bindings/interrupt-controller/irq.h> 175 #include <dt-bindings/interrupt-controller/arm-gic.h> 176 #include <dt-bindings/clock/dra7.h> 177 178 mac_sw: switch@0 { 179 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; 180 reg = <0x0 0x4000>; 181 ranges = <0 0 0x4000>; 182 clocks = <&gmac_main_clk>; 183 clock-names = "fck"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 syscon = <&scm_conf>; 187 188 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 193 194 ethernet-ports { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 cpsw_port1: port@1 { 199 reg = <1>; 200 label = "port1"; 201 mac-address = [ 00 00 00 00 00 00 ]; 202 phys = <&phy_gmii_sel 1>; 203 phy-handle = <ðphy0_sw>; 204 phy-mode = "rgmii"; 205 ti,dual-emac-pvid = <1>; 206 }; 207 208 cpsw_port2: port@2 { 209 reg = <2>; 210 label = "wan"; 211 mac-address = [ 00 00 00 00 00 00 ]; 212 phys = <&phy_gmii_sel 2>; 213 phy-handle = <ðphy1_sw>; 214 phy-mode = "rgmii"; 215 ti,dual-emac-pvid = <2>; 216 }; 217 }; 218 219 davinci_mdio_sw: mdio@1000 { 220 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 221 reg = <0x1000 0x100>; 222 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 223 clock-names = "fck"; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 bus_freq = <1000000>; 227 228 ethphy0_sw: ethernet-phy@0 { 229 reg = <0>; 230 }; 231 232 ethphy1_sw: ethernet-phy@1 { 233 reg = <1>; 234 }; 235 }; 236 237 cpts { 238 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 239 clock-names = "cpts"; 240 }; 241 }; 242