xref: /linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml (revision b86761ff6374813cdf64ffd6b95ddd1813c435d8) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
9
10maintainers:
11  - Alexandre Torgue <alexandre.torgue@foss.st.com>
12  - Christophe Roullier <christophe.roullier@foss.st.com>
13
14description:
15  This file documents platform glue layer for stmmac.
16
17# We need a select here so we don't match all nodes with 'snps,dwmac'
18select:
19  properties:
20    compatible:
21      contains:
22        enum:
23          - st,stm32-dwmac
24          - st,stm32mp1-dwmac
25  required:
26    - compatible
27
28allOf:
29  - $ref: snps,dwmac.yaml#
30
31properties:
32  compatible:
33    oneOf:
34      - items:
35          - enum:
36              - st,stm32mp1-dwmac
37          - const: snps,dwmac-4.20a
38      - items:
39          - enum:
40              - st,stm32-dwmac
41          - const: snps,dwmac-4.10a
42      - items:
43          - enum:
44              - st,stm32-dwmac
45          - const: snps,dwmac-3.50a
46
47  reg: true
48
49  reg-names:
50    items:
51      - const: stmmaceth
52
53  clocks:
54    minItems: 3
55    items:
56      - description: GMAC main clock
57      - description: MAC TX clock
58      - description: MAC RX clock
59      - description: For MPU family, used for power mode
60      - description: For MPU family, used for PHY without quartz
61      - description: PTP clock
62
63  clock-names:
64    minItems: 3
65    maxItems: 6
66    contains:
67      enum:
68        - stmmaceth
69        - mac-clk-tx
70        - mac-clk-rx
71        - ethstp
72        - eth-ck
73        - ptp_ref
74
75  st,syscon:
76    $ref: /schemas/types.yaml#/definitions/phandle-array
77    items:
78      - items:
79          - description: phandle to the syscon node which encompases the glue register
80          - description: offset of the control register
81    description:
82      Should be phandle/offset pair. The phandle to the syscon node which
83      encompases the glue register, and the offset of the control register
84
85  st,ext-phyclk:
86    description:
87      set this property in RMII mode when you have PHY without crystal 50MHz and want to
88      select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
89      RCC clock instead of ETH_CLK125.
90    type: boolean
91
92  st,eth-clk-sel:
93    description:
94      set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
95    type: boolean
96
97  st,eth-ref-clk-sel:
98    description:
99      set this property in RMII mode when you have PHY without crystal 50MHz and want to
100      select RCC clock instead of ETH_REF_CLK.
101    type: boolean
102
103required:
104  - compatible
105  - clocks
106  - clock-names
107  - st,syscon
108
109unevaluatedProperties: false
110
111examples:
112  - |
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114    #include <dt-bindings/clock/stm32mp1-clks.h>
115    #include <dt-bindings/reset/stm32mp1-resets.h>
116    #include <dt-bindings/mfd/stm32h7-rcc.h>
117    //Example 1
118     ethernet0: ethernet@5800a000 {
119           compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
120           reg = <0x5800a000 0x2000>;
121           reg-names = "stmmaceth";
122           interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
123           interrupt-names = "macirq";
124           clock-names = "stmmaceth",
125                     "mac-clk-tx",
126                     "mac-clk-rx",
127                     "ethstp",
128                     "eth-ck";
129           clocks = <&rcc ETHMAC>,
130                <&rcc ETHTX>,
131                <&rcc ETHRX>,
132                <&rcc ETHSTP>,
133                <&rcc ETHCK_K>;
134           st,syscon = <&syscfg 0x4>;
135           snps,pbl = <2>;
136           snps,axi-config = <&stmmac_axi_config_0>;
137           snps,tso;
138           phy-mode = "rgmii";
139       };
140
141  - |
142    //Example 2 (MCU example)
143     ethernet1: ethernet@40028000 {
144           compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
145           reg = <0x40028000 0x8000>;
146           reg-names = "stmmaceth";
147           interrupts = <0 61 0>, <0 62 0>;
148           interrupt-names = "macirq", "eth_wake_irq";
149           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
150           clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
151           st,syscon = <&syscfg 0x4>;
152           snps,pbl = <8>;
153           snps,mixed-burst;
154           phy-mode = "mii";
155       };
156
157  - |
158    //Example 3
159     ethernet2: ethernet@40027000 {
160           compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
161           reg = <0x40028000 0x8000>;
162           reg-names = "stmmaceth";
163           interrupts = <61>;
164           interrupt-names = "macirq";
165           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
166           clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
167           st,syscon = <&syscfg 0x4>;
168           snps,pbl = <8>;
169           phy-mode = "mii";
170       };
171