xref: /linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml (revision a6a6a98094116b60e5523a571d9443c53325f5b1) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
9
10maintainers:
11  - Alexandre Torgue <alexandre.torgue@foss.st.com>
12  - Christophe Roullier <christophe.roullier@foss.st.com>
13
14description:
15  This file documents platform glue layer for stmmac.
16
17# We need a select here so we don't match all nodes with 'snps,dwmac'
18select:
19  properties:
20    compatible:
21      contains:
22        enum:
23          - st,stm32-dwmac
24          - st,stm32mp1-dwmac
25          - st,stm32mp13-dwmac
26  required:
27    - compatible
28
29properties:
30  compatible:
31    oneOf:
32      - items:
33          - enum:
34              - st,stm32mp1-dwmac
35              - st,stm32mp13-dwmac
36          - const: snps,dwmac-4.20a
37      - items:
38          - enum:
39              - st,stm32-dwmac
40          - const: snps,dwmac-4.10a
41      - items:
42          - enum:
43              - st,stm32-dwmac
44          - const: snps,dwmac-3.50a
45
46  reg: true
47
48  reg-names:
49    items:
50      - const: stmmaceth
51
52  clocks:
53    minItems: 3
54    items:
55      - description: GMAC main clock
56      - description: MAC TX clock
57      - description: MAC RX clock
58      - description: For MPU family, used for power mode
59      - description: For MPU family, used for PHY without quartz
60      - description: PTP clock
61
62  clock-names:
63    minItems: 3
64    maxItems: 6
65    contains:
66      enum:
67        - stmmaceth
68        - mac-clk-tx
69        - mac-clk-rx
70        - ethstp
71        - eth-ck
72        - ptp_ref
73
74  st,syscon:
75    $ref: /schemas/types.yaml#/definitions/phandle-array
76    items:
77      - minItems: 2
78        items:
79          - description: phandle to the syscon node which encompases the glue register
80          - description: offset of the control register
81          - description: field to set mask in register
82    description:
83      Should be phandle/offset pair. The phandle to the syscon node which
84      encompases the glue register, the offset of the control register and
85      the mask to set bitfield in control register
86
87  st,ext-phyclk:
88    description:
89      set this property in RMII mode when you have PHY without crystal 50MHz and want to
90      select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
91      RCC clock instead of ETH_CLK125.
92    type: boolean
93
94  st,eth-clk-sel:
95    description:
96      set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
97    type: boolean
98
99  st,eth-ref-clk-sel:
100    description:
101      set this property in RMII mode when you have PHY without crystal 50MHz and want to
102      select RCC clock instead of ETH_REF_CLK.
103    type: boolean
104
105  access-controllers:
106    minItems: 1
107    maxItems: 2
108
109required:
110  - compatible
111  - clocks
112  - clock-names
113  - st,syscon
114
115unevaluatedProperties: false
116
117allOf:
118  - $ref: snps,dwmac.yaml#
119  - if:
120      properties:
121        compatible:
122          contains:
123            enum:
124              - st,stm32mp1-dwmac
125              - st,stm32-dwmac
126    then:
127      properties:
128        st,syscon:
129          items:
130            minItems: 2
131            maxItems: 2
132
133  - if:
134      properties:
135        compatible:
136          contains:
137            enum:
138              - st,stm32mp13-dwmac
139    then:
140      properties:
141        st,syscon:
142          items:
143            minItems: 3
144            maxItems: 3
145
146examples:
147  - |
148    #include <dt-bindings/interrupt-controller/arm-gic.h>
149    #include <dt-bindings/clock/stm32mp1-clks.h>
150    //Example 1
151     ethernet0: ethernet@5800a000 {
152           compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
153           reg = <0x5800a000 0x2000>;
154           reg-names = "stmmaceth";
155           interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
156           interrupt-names = "macirq";
157           clock-names = "stmmaceth",
158                     "mac-clk-tx",
159                     "mac-clk-rx",
160                     "ethstp",
161                     "eth-ck";
162           clocks = <&rcc ETHMAC>,
163                <&rcc ETHTX>,
164                <&rcc ETHRX>,
165                <&rcc ETHSTP>,
166                <&rcc ETHCK_K>;
167           st,syscon = <&syscfg 0x4>;
168           snps,pbl = <2>;
169           snps,axi-config = <&stmmac_axi_config_0>;
170           snps,tso;
171           phy-mode = "rgmii";
172       };
173
174  - |
175    //Example 2 (MCU example)
176     ethernet1: ethernet@40028000 {
177           compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
178           reg = <0x40028000 0x8000>;
179           reg-names = "stmmaceth";
180           interrupts = <0 61 0>, <0 62 0>;
181           interrupt-names = "macirq", "eth_wake_irq";
182           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
183           clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
184           st,syscon = <&syscfg 0x4>;
185           snps,pbl = <8>;
186           snps,mixed-burst;
187           phy-mode = "mii";
188       };
189
190  - |
191    //Example 3
192     ethernet2: ethernet@40027000 {
193           compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
194           reg = <0x40028000 0x8000>;
195           reg-names = "stmmaceth";
196           interrupts = <61>;
197           interrupt-names = "macirq";
198           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
199           clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
200           st,syscon = <&syscfg 0x4>;
201           snps,pbl = <8>;
202           phy-mode = "mii";
203       };
204