1STMicroelectronics SoC DWMAC glue layer controller 2 3This file documents differences between the core properties in 4Documentation/devicetree/bindings/net/stmmac.txt 5and what is needed on STi platforms to program the stmmac glue logic. 6 7The device node has following properties. 8 9Required properties: 10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", 11 "st,stih407-dwmac", "st,stid127-dwmac". 12 - reg : Offset of the glue configuration register map in system 13 configuration regmap pointed by st,syscon property and size. 14 - st,syscon : Should be phandle to system configuration node which 15 encompases this glue registers. 16 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control 17 register available on STiH407 SoC. 18 - sti-ethconf: this is the gmac glue logic register to enable the GMAC, 19 select among the different modes and program the clk retiming. 20 - pinctrl-0: pin-control for all the MII mode supported. 21 22Optional properties: 23 - resets : phandle pointing to the system reset controller with correct 24 reset line index for ethernet reset. 25 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or 26 MAC can generate it. 27 - st,tx-retime-src: This specifies which clk is wired up to the mac for 28 retimeing tx lines. This is totally board dependent and can take one of the 29 posssible values from "txclk", "clk_125" or "clkgen". 30 If not passed, the internal clock will be used by default. 31 - sti-ethclk: this is the phy clock. 32 - sti-clkconf: this is an extra sysconfig register, available in new SoCs, 33 to program the clk retiming. 34 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. 35 STiH407. 36 37Example: 38 39ethernet0: dwmac@9630000 { 40 device_type = "network"; 41 status = "disabled"; 42 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 43 reg = <0x9630000 0x8000>, <0x80 0x4>; 44 reg-names = "stmmaceth", "sti-ethconf"; 45 46 st,syscon = <&syscfg_sbc_reg>; 47 st,gmac_en; 48 resets = <&softreset STIH407_ETH1_SOFTRESET>; 49 reset-names = "stmmaceth"; 50 51 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 52 <GIC_SPI 99 IRQ_TYPE_NONE>, 53 <GIC_SPI 100 IRQ_TYPE_NONE>; 54 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 55 56 snps,pbl = <32>; 57 snps,mixed-burst; 58 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_rgmii1>; 61 62 clock-names = "stmmaceth", "sti-ethclk"; 63 clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, 64 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; 65}; 66