xref: /linux/Documentation/devicetree/bindings/net/sti-dwmac.txt (revision 53b26b9bc9a547bf10135a8079e5ae88f354b9f6)
1d15891caSSrinivas KandagatlaSTMicroelectronics SoC DWMAC glue layer controller
2d15891caSSrinivas Kandagatla
3*53b26b9bSGiuseppe CAVALLAROThis file documents differences between the core properties in
4*53b26b9bSGiuseppe CAVALLARODocumentation/devicetree/bindings/net/stmmac.txt
5*53b26b9bSGiuseppe CAVALLAROand what is needed on STi platforms to program the stmmac glue logic.
6*53b26b9bSGiuseppe CAVALLARO
7d15891caSSrinivas KandagatlaThe device node has following properties.
8d15891caSSrinivas Kandagatla
9d15891caSSrinivas KandagatlaRequired properties:
10160e1fd1SGiuseppe CAVALLARO - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
11*53b26b9bSGiuseppe CAVALLARO   "st,stih407-dwmac", "st,stid127-dwmac".
12d15891caSSrinivas Kandagatla - reg : Offset of the glue configuration register map in system
13d15891caSSrinivas Kandagatla   configuration regmap pointed by st,syscon property and size.
14d15891caSSrinivas Kandagatla - st,syscon : Should be phandle to system configuration node which
15d15891caSSrinivas Kandagatla   encompases this glue registers.
16*53b26b9bSGiuseppe CAVALLARO - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
17*53b26b9bSGiuseppe CAVALLARO   register available on STiH407 SoC.
18*53b26b9bSGiuseppe CAVALLARO - sti-ethconf: this is the gmac glue logic register to enable the GMAC,
19*53b26b9bSGiuseppe CAVALLARO   select among the different modes and program the clk retiming.
20*53b26b9bSGiuseppe CAVALLARO - pinctrl-0: pin-control for all the MII mode supported.
21d15891caSSrinivas Kandagatla
22*53b26b9bSGiuseppe CAVALLAROOptional properties:
23*53b26b9bSGiuseppe CAVALLARO - resets : phandle pointing to the system reset controller with correct
24*53b26b9bSGiuseppe CAVALLARO   reset line index for ethernet reset.
25*53b26b9bSGiuseppe CAVALLARO - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
26*53b26b9bSGiuseppe CAVALLARO   MAC can generate it.
27*53b26b9bSGiuseppe CAVALLARO - st,tx-retime-src: This specifies which clk is wired up to the mac for
28*53b26b9bSGiuseppe CAVALLARO   retimeing tx lines. This is totally board dependent and can take one of the
29*53b26b9bSGiuseppe CAVALLARO   posssible values from "txclk", "clk_125" or "clkgen".
30*53b26b9bSGiuseppe CAVALLARO   If not passed, the internal clock will be used by default.
31*53b26b9bSGiuseppe CAVALLARO - sti-ethclk: this is the phy clock.
32*53b26b9bSGiuseppe CAVALLARO - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
33*53b26b9bSGiuseppe CAVALLARO   to program the clk retiming.
34*53b26b9bSGiuseppe CAVALLARO - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
35*53b26b9bSGiuseppe CAVALLARO   STiH407.
36d15891caSSrinivas Kandagatla
37d15891caSSrinivas KandagatlaExample:
38d15891caSSrinivas Kandagatla
39*53b26b9bSGiuseppe CAVALLAROethernet0: dwmac@9630000 {
40d15891caSSrinivas Kandagatla	device_type = "network";
41*53b26b9bSGiuseppe CAVALLARO	status = "disabled";
42*53b26b9bSGiuseppe CAVALLARO	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
43*53b26b9bSGiuseppe CAVALLARO	reg = <0x9630000 0x8000>, <0x80 0x4>;
44d15891caSSrinivas Kandagatla	reg-names = "stmmaceth", "sti-ethconf";
45d15891caSSrinivas Kandagatla
46*53b26b9bSGiuseppe CAVALLARO	st,syscon = <&syscfg_sbc_reg>;
47*53b26b9bSGiuseppe CAVALLARO	st,gmac_en;
48*53b26b9bSGiuseppe CAVALLARO	resets = <&softreset STIH407_ETH1_SOFTRESET>;
49*53b26b9bSGiuseppe CAVALLARO	reset-names = "stmmaceth";
50*53b26b9bSGiuseppe CAVALLARO
51*53b26b9bSGiuseppe CAVALLARO	interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
52*53b26b9bSGiuseppe CAVALLARO		     <GIC_SPI 99 IRQ_TYPE_NONE>,
53*53b26b9bSGiuseppe CAVALLARO		     <GIC_SPI 100 IRQ_TYPE_NONE>;
54*53b26b9bSGiuseppe CAVALLARO	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
55d15891caSSrinivas Kandagatla
56d15891caSSrinivas Kandagatla	snps,pbl = <32>;
57d15891caSSrinivas Kandagatla	snps,mixed-burst;
58d15891caSSrinivas Kandagatla
59d15891caSSrinivas Kandagatla	pinctrl-names = "default";
60*53b26b9bSGiuseppe CAVALLARO	pinctrl-0 = <&pinctrl_rgmii1>;
61*53b26b9bSGiuseppe CAVALLARO
62*53b26b9bSGiuseppe CAVALLARO	clock-names = "stmmaceth", "sti-ethclk";
63*53b26b9bSGiuseppe CAVALLARO	clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
64*53b26b9bSGiuseppe CAVALLARO		 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
65d15891caSSrinivas Kandagatla};
66