xref: /linux/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml (revision e7d759f31ca295d589f7420719c311870bb3166f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 StarFive Technology Co., Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: StarFive JH7110 DWMAC glue layer
9
10maintainers:
11  - Emil Renner Berthing <kernel@esmil.dk>
12  - Samin Guo <samin.guo@starfivetech.com>
13
14select:
15  properties:
16    compatible:
17      contains:
18        enum:
19          - starfive,jh7110-dwmac
20  required:
21    - compatible
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - starfive,jh7110-dwmac
28      - const: snps,dwmac-5.20
29
30  reg:
31    maxItems: 1
32
33  clocks:
34    items:
35      - description: GMAC main clock
36      - description: GMAC AHB clock
37      - description: PTP clock
38      - description: TX clock
39      - description: GTX clock
40
41  clock-names:
42    items:
43      - const: stmmaceth
44      - const: pclk
45      - const: ptp_ref
46      - const: tx
47      - const: gtx
48
49  interrupts:
50    minItems: 3
51    maxItems: 3
52
53  interrupt-names:
54    minItems: 3
55    maxItems: 3
56
57  resets:
58    items:
59      - description: MAC Reset signal.
60      - description: AHB Reset signal.
61
62  reset-names:
63    items:
64      - const: stmmaceth
65      - const: ahb
66
67  starfive,tx-use-rgmii-clk:
68    description:
69      Tx clock is provided by external rgmii clock.
70    type: boolean
71
72  starfive,syscon:
73    $ref: /schemas/types.yaml#/definitions/phandle-array
74    items:
75      - items:
76          - description: phandle to syscon that configures phy mode
77          - description: Offset of phy mode selection
78          - description: Shift of phy mode selection
79    description:
80      A phandle to syscon with two arguments that configure phy mode.
81      The argument one is the offset of phy mode selection, the
82      argument two is the shift of phy mode selection.
83
84required:
85  - compatible
86  - reg
87  - clocks
88  - clock-names
89  - interrupts
90  - interrupt-names
91  - resets
92  - reset-names
93
94allOf:
95  - $ref: snps,dwmac.yaml#
96
97unevaluatedProperties: false
98
99examples:
100  - |
101    ethernet@16030000 {
102        compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
103        reg = <0x16030000 0x10000>;
104        clocks = <&clk 3>, <&clk 2>, <&clk 109>,
105                 <&clk 6>, <&clk 111>;
106        clock-names = "stmmaceth", "pclk", "ptp_ref",
107                      "tx", "gtx";
108        resets = <&rst 1>, <&rst 2>;
109        reset-names = "stmmaceth", "ahb";
110        interrupts = <7>, <6>, <5>;
111        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
112        phy-mode = "rgmii-id";
113        snps,multicast-filter-bins = <64>;
114        snps,perfect-filter-entries = <8>;
115        rx-fifo-depth = <2048>;
116        tx-fifo-depth = <2048>;
117        snps,fixed-burst;
118        snps,no-pbl-x8;
119        snps,tso;
120        snps,force_thresh_dma_mode;
121        snps,axi-config = <&stmmac_axi_setup>;
122        snps,en-tx-lpi-clockgating;
123        snps,txpbl = <16>;
124        snps,rxpbl = <16>;
125        starfive,syscon = <&aon_syscon 0xc 0x12>;
126        phy-handle = <&phy0>;
127
128        mdio {
129            #address-cells = <1>;
130            #size-cells = <0>;
131            compatible = "snps,dwmac-mdio";
132
133            phy0: ethernet-phy@0 {
134                reg = <0>;
135            };
136        };
137
138        stmmac_axi_setup: stmmac-axi-config {
139            snps,lpi_en;
140            snps,wr_osr_lmt = <4>;
141            snps,rd_osr_lmt = <4>;
142            snps,blen = <256 128 64 32 0 0 0>;
143        };
144    };
145