1Altera SOCFPGA SoC DWMAC controller 2 3This is a variant of the dwmac/stmmac driver an inherits all descriptions 4present in Documentation/devicetree/bindings/net/stmmac.txt. 5 6The device node has additional properties: 7 8Required properties: 9 - compatible : Should contain "altr,socfpga-stmmac" along with 10 "snps,dwmac" and any applicable more detailed 11 designware version numbers documented in stmmac.txt 12 - altr,sysmgr-syscon : Should be the phandle to the system manager node that 13 encompasses the glue register, the register offset, and the register shift. 14 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock 15 for ptp ref clk. This affects all emacs as the clock is common. 16 17Optional properties: 18altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if 19 DWMAC controller is connected emac splitter. 20phy-mode: The phy mode the ethernet operates in 21altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter 22 23This device node has additional phandle dependency, the sgmii converter: 24 25Required properties: 26 - compatible : Should be altr,gmii-to-sgmii-2.0 27 - reg-names : Should be "eth_tse_control_port" 28 29Example: 30 31gmii_to_sgmii_converter: phy@100000240 { 32 compatible = "altr,gmii-to-sgmii-2.0"; 33 reg = <0x00000001 0x00000240 0x00000008>, 34 <0x00000001 0x00000200 0x00000040>; 35 reg-names = "eth_tse_control_port"; 36 clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; 37 clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; 38}; 39 40gmac0: ethernet@ff700000 { 41 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 42 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 43 reg = <0xff700000 0x2000>; 44 interrupts = <0 115 4>; 45 interrupt-names = "macirq"; 46 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 47 clocks = <&emac_0_clk>; 48 clock-names = "stmmaceth"; 49 phy-mode = "sgmii"; 50 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; 51}; 52