xref: /linux/Documentation/devicetree/bindings/net/renesas,ether.yaml (revision 95298d63c67673c654c08952672d016212b26054) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,ether.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Electronics SH EtherMAC
8
9allOf:
10  - $ref: ethernet-controller.yaml#
11
12maintainers:
13  - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - renesas,gether-r8a7740   # device is a part of R8A7740 SoC
21              - renesas,gether-r8a77980  # device is a part of R8A77980 SoC
22              - renesas,ether-r7s72100   # device is a part of R7S72100 SoC
23              - renesas,ether-r7s9210    # device is a part of R7S9210 SoC
24      - items:
25          - enum:
26              - renesas,ether-r8a7778    # device is a part of R8A7778 SoC
27              - renesas,ether-r8a7779    # device is a part of R8A7779 SoC
28          - enum:
29              - renesas,rcar-gen1-ether  # a generic R-Car Gen1 device
30      - items:
31          - enum:
32              - renesas,ether-r8a7742    # device is a part of R8A7742 SoC
33              - renesas,ether-r8a7743    # device is a part of R8A7743 SoC
34              - renesas,ether-r8a7745    # device is a part of R8A7745 SoC
35              - renesas,ether-r8a7790    # device is a part of R8A7790 SoC
36              - renesas,ether-r8a7791    # device is a part of R8A7791 SoC
37              - renesas,ether-r8a7793    # device is a part of R8A7793 SoC
38              - renesas,ether-r8a7794    # device is a part of R8A7794 SoC
39          - enum:
40              - renesas,rcar-gen2-ether  # a generic R-Car Gen2 or RZ/G1 device
41
42  reg:
43    items:
44      - description: E-DMAC/feLic registers
45      - description: TSU registers
46    minItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  '#address-cells':
52    description: number of address cells for the MDIO bus
53    const: 1
54
55  '#size-cells':
56    description: number of size cells on the MDIO bus
57    const: 0
58
59  clocks:
60    maxItems: 1
61
62  pinctrl-0: true
63
64  pinctrl-names: true
65
66  renesas,no-ether-link:
67    type: boolean
68    description:
69      specify when a board does not provide a proper Ether LINK signal
70
71  renesas,ether-link-active-low:
72    type: boolean
73    description:
74      specify when the Ether LINK signal is active-low instead of normal
75      active-high
76
77required:
78  - compatible
79  - reg
80  - interrupts
81  - phy-mode
82  - phy-handle
83  - '#address-cells'
84  - '#size-cells'
85  - clocks
86  - pinctrl-0
87
88examples:
89  # Lager board
90  - |
91    #include <dt-bindings/clock/r8a7790-clock.h>
92    #include <dt-bindings/interrupt-controller/irq.h>
93
94    ethernet@ee700000 {
95        compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
96        reg = <0xee700000 0x400>;
97        interrupt-parent = <&gic>;
98        interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
99        clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
100        phy-mode = "rmii";
101        phy-handle = <&phy1>;
102        pinctrl-0 = <&ether_pins>;
103        pinctrl-names = "default";
104        renesas,ether-link-active-low;
105        #address-cells = <1>;
106        #size-cells = <0>;
107
108        phy1: ethernet-phy@1 {
109            reg = <1>;
110            interrupt-parent = <&irqc0>;
111            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
112            pinctrl-0 = <&phy1_pins>;
113            pinctrl-names = "default";
114        };
115    };
116