1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm IPQ packet process engine (PPE) 8 9maintainers: 10 - Luo Jie <quic_luoj@quicinc.com> 11 - Lei Wei <quic_leiwei@quicinc.com> 12 - Suruchi Agarwal <quic_suruchia@quicinc.com> 13 - Pavithra R <quic_pavir@quicinc.com> 14 15description: | 16 The Ethernet functionality in the PPE (Packet Process Engine) is comprised 17 of three components, the switch core, port wrapper and Ethernet DMA. 18 19 The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and 20 two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet 21 port to host CPU communication using Ethernet DMA. The other is used 22 communicating to the EIP engine which is used for IPsec offload. On the 23 IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external 24 Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue 25 Management) and SCH (Scheduler) modules for supporting the packet processing. 26 27 The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) 28 supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There 29 are 3 UNIPHY (PCS) instances supported on the IPQ9574. 30 31 Ethernet DMA is used to transmit and receive packets between the six Ethernet 32 ports and ARM host CPU. 33 34 The follow diagram shows the PPE hardware block along with its connectivity 35 to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, 36 NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY 37 connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an 38 example. 39 40 +---------+ 41 | 48 MHZ | 42 +----+----+ 43 |(clock) 44 v 45 +----+----+ 46 +------| CMN PLL | 47 | +----+----+ 48 | |(clock) 49 | v 50 | +----+----+ +----+----+ (clock) +----+----+ 51 | +---| NSSCC | | GCC |--------->| MDIO | 52 | | +----+----+ +----+----+ +----+----+ 53 | | |(clock & reset) |(clock) 54 | | v v 55 | | +----+---------------------+--+----------+----------+---------+ 56 | | | +-----+ |EDMA FIFO | | EIP FIFO| 57 | | | | SCH | +----------+ +---------+ 58 | | | +-----+ | | | 59 | | | +------+ +------+ +-------------------+ | 60 | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | 61 | | | +------+ +------+ +-------------------+ | 62 | | | | | 63 | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | 64 | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | 65 | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | 66 | | | | | | | | | | 67 | | +-----+---------+---------+---------+---------+---------+-----+ 68 | | | | | | | | 69 | | +---+---------+---------+---------+---+ +---+---+ +---+---+ 70 +--+---->| PCS0 | | PCS1 | | PCS2 | 71 |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ 72 | | | | | | | 73 | +---+---------+---------+---------+---+ +---+---+ +---+---+ 74 +------->| QCA8075 PHY | | PHY4 | | PHY5 | 75 (clock) +-------------------------------------+ +-------+ +-------+ 76 77properties: 78 compatible: 79 enum: 80 - qcom,ipq9574-ppe 81 82 reg: 83 maxItems: 1 84 85 clocks: 86 items: 87 - description: PPE core clock 88 - description: PPE APB (Advanced Peripheral Bus) clock 89 - description: PPE IPE (Ingress Process Engine) clock 90 - description: PPE BM, QM and scheduler clock 91 92 clock-names: 93 items: 94 - const: ppe 95 - const: apb 96 - const: ipe 97 - const: btq 98 99 resets: 100 maxItems: 1 101 description: PPE reset, which is necessary before configuring PPE hardware 102 103 interrupts: 104 maxItems: 1 105 description: PPE switch miscellaneous interrupt 106 107 interconnects: 108 items: 109 - description: Bus interconnect path leading to PPE switch core function 110 - description: Bus interconnect path leading to PPE register access 111 - description: Bus interconnect path leading to QoS generation 112 - description: Bus interconnect path leading to timeout reference 113 - description: Bus interconnect path leading to NSS NOC from memory NOC 114 - description: Bus interconnect path leading to memory NOC from NSS NOC 115 - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC 116 117 interconnect-names: 118 items: 119 - const: ppe 120 - const: ppe_cfg 121 - const: qos_gen 122 - const: timeout_ref 123 - const: nssnoc_memnoc 124 - const: memnoc_nssnoc 125 - const: memnoc_nssnoc_1 126 127 ethernet-dma: 128 type: object 129 additionalProperties: false 130 description: 131 EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM 132 host CPU. There are 32 TX descriptor rings, 32 TX completion rings, 133 24 RX descriptor rings and 8 RX fill rings supported. 134 135 properties: 136 clocks: 137 items: 138 - description: EDMA system clock 139 - description: EDMA APB (Advanced Peripheral Bus) clock 140 141 clock-names: 142 items: 143 - const: sys 144 - const: apb 145 146 resets: 147 maxItems: 1 148 description: EDMA reset 149 150 interrupts: 151 minItems: 65 152 maxItems: 65 153 154 interrupt-names: 155 minItems: 65 156 maxItems: 65 157 items: 158 oneOf: 159 - pattern: '^txcmpl_([1-2]?[0-9]|3[01])$' 160 - pattern: '^rxfill_[0-7]$' 161 - pattern: '^rxdesc_(1?[0-9]|2[0-3])$' 162 - const: misc 163 description: 164 Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts. 165 Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts. 166 Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts. 167 Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. 168 169 required: 170 - clocks 171 - clock-names 172 - resets 173 - interrupts 174 - interrupt-names 175 176 ethernet-ports: 177 patternProperties: 178 "^ethernet-port@[1-6]+$": 179 type: object 180 unevaluatedProperties: false 181 $ref: ethernet-switch-port.yaml# 182 183 properties: 184 reg: 185 minimum: 1 186 maximum: 6 187 description: PPE Ethernet port ID 188 189 clocks: 190 items: 191 - description: Port MAC clock 192 - description: Port RX clock 193 - description: Port TX clock 194 195 clock-names: 196 items: 197 - const: mac 198 - const: rx 199 - const: tx 200 201 resets: 202 items: 203 - description: Port MAC reset 204 - description: Port RX reset 205 - description: Port TX reset 206 207 reset-names: 208 items: 209 - const: mac 210 - const: rx 211 - const: tx 212 213 required: 214 - reg 215 - clocks 216 - clock-names 217 - resets 218 - reset-names 219 220required: 221 - compatible 222 - reg 223 - clocks 224 - clock-names 225 - resets 226 - interconnects 227 - interconnect-names 228 - ethernet-dma 229 230allOf: 231 - $ref: ethernet-switch.yaml 232 233unevaluatedProperties: false 234 235examples: 236 - | 237 #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 238 #include <dt-bindings/clock/qcom,ipq9574-nsscc.h> 239 #include <dt-bindings/interconnect/qcom,ipq9574.h> 240 #include <dt-bindings/interrupt-controller/arm-gic.h> 241 #include <dt-bindings/reset/qcom,ipq9574-nsscc.h> 242 243 ethernet-switch@3a000000 { 244 compatible = "qcom,ipq9574-ppe"; 245 reg = <0x3a000000 0xbef800>; 246 clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>, 247 <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, 248 <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, 249 <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; 250 clock-names = "ppe", 251 "apb", 252 "ipe", 253 "btq"; 254 resets = <&nsscc PPE_FULL_RESET>; 255 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>; 256 interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, 257 <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, 258 <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, 259 <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, 260 <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, 261 <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, 262 <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; 263 interconnect-names = "ppe", 264 "ppe_cfg", 265 "qos_gen", 266 "timeout_ref", 267 "nssnoc_memnoc", 268 "memnoc_nssnoc", 269 "memnoc_nssnoc_1"; 270 271 ethernet-dma { 272 clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>, 273 <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; 274 clock-names = "sys", 275 "apb"; 276 resets = <&nsscc EDMA_HW_RESET>; 277 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "txcmpl_0", 343 "txcmpl_1", 344 "txcmpl_2", 345 "txcmpl_3", 346 "txcmpl_4", 347 "txcmpl_5", 348 "txcmpl_6", 349 "txcmpl_7", 350 "txcmpl_8", 351 "txcmpl_9", 352 "txcmpl_10", 353 "txcmpl_11", 354 "txcmpl_12", 355 "txcmpl_13", 356 "txcmpl_14", 357 "txcmpl_15", 358 "txcmpl_16", 359 "txcmpl_17", 360 "txcmpl_18", 361 "txcmpl_19", 362 "txcmpl_20", 363 "txcmpl_21", 364 "txcmpl_22", 365 "txcmpl_23", 366 "txcmpl_24", 367 "txcmpl_25", 368 "txcmpl_26", 369 "txcmpl_27", 370 "txcmpl_28", 371 "txcmpl_29", 372 "txcmpl_30", 373 "txcmpl_31", 374 "rxfill_0", 375 "rxfill_1", 376 "rxfill_2", 377 "rxfill_3", 378 "rxfill_4", 379 "rxfill_5", 380 "rxfill_6", 381 "rxfill_7", 382 "rxdesc_0", 383 "rxdesc_1", 384 "rxdesc_2", 385 "rxdesc_3", 386 "rxdesc_4", 387 "rxdesc_5", 388 "rxdesc_6", 389 "rxdesc_7", 390 "rxdesc_8", 391 "rxdesc_9", 392 "rxdesc_10", 393 "rxdesc_11", 394 "rxdesc_12", 395 "rxdesc_13", 396 "rxdesc_14", 397 "rxdesc_15", 398 "rxdesc_16", 399 "rxdesc_17", 400 "rxdesc_18", 401 "rxdesc_19", 402 "rxdesc_20", 403 "rxdesc_21", 404 "rxdesc_22", 405 "rxdesc_23", 406 "misc"; 407 }; 408 409 ethernet-ports { 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 ethernet-port@1 { 414 reg = <1>; 415 phy-mode = "qsgmii"; 416 managed = "in-band-status"; 417 phy-handle = <&phy0>; 418 pcs-handle = <&pcs0_ch0>; 419 clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, 420 <&nsscc NSS_CC_PORT1_RX_CLK>, 421 <&nsscc NSS_CC_PORT1_TX_CLK>; 422 clock-names = "mac", 423 "rx", 424 "tx"; 425 resets = <&nsscc PORT1_MAC_ARES>, 426 <&nsscc PORT1_RX_ARES>, 427 <&nsscc PORT1_TX_ARES>; 428 reset-names = "mac", 429 "rx", 430 "tx"; 431 }; 432 433 ethernet-port@2 { 434 reg = <2>; 435 phy-mode = "qsgmii"; 436 managed = "in-band-status"; 437 phy-handle = <&phy1>; 438 pcs-handle = <&pcs0_ch1>; 439 clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, 440 <&nsscc NSS_CC_PORT2_RX_CLK>, 441 <&nsscc NSS_CC_PORT2_TX_CLK>; 442 clock-names = "mac", 443 "rx", 444 "tx"; 445 resets = <&nsscc PORT2_MAC_ARES>, 446 <&nsscc PORT2_RX_ARES>, 447 <&nsscc PORT2_TX_ARES>; 448 reset-names = "mac", 449 "rx", 450 "tx"; 451 }; 452 453 ethernet-port@3 { 454 reg = <3>; 455 phy-mode = "qsgmii"; 456 managed = "in-band-status"; 457 phy-handle = <&phy2>; 458 pcs-handle = <&pcs0_ch2>; 459 clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, 460 <&nsscc NSS_CC_PORT3_RX_CLK>, 461 <&nsscc NSS_CC_PORT3_TX_CLK>; 462 clock-names = "mac", 463 "rx", 464 "tx"; 465 resets = <&nsscc PORT3_MAC_ARES>, 466 <&nsscc PORT3_RX_ARES>, 467 <&nsscc PORT3_TX_ARES>; 468 reset-names = "mac", 469 "rx", 470 "tx"; 471 }; 472 473 ethernet-port@4 { 474 reg = <4>; 475 phy-mode = "qsgmii"; 476 managed = "in-band-status"; 477 phy-handle = <&phy3>; 478 pcs-handle = <&pcs0_ch3>; 479 clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, 480 <&nsscc NSS_CC_PORT4_RX_CLK>, 481 <&nsscc NSS_CC_PORT4_TX_CLK>; 482 clock-names = "mac", 483 "rx", 484 "tx"; 485 resets = <&nsscc PORT4_MAC_ARES>, 486 <&nsscc PORT4_RX_ARES>, 487 <&nsscc PORT4_TX_ARES>; 488 reset-names = "mac", 489 "rx", 490 "tx"; 491 }; 492 493 ethernet-port@5 { 494 reg = <5>; 495 phy-mode = "usxgmii"; 496 managed = "in-band-status"; 497 phy-handle = <&phy4>; 498 pcs-handle = <&pcs1_ch0>; 499 clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, 500 <&nsscc NSS_CC_PORT5_RX_CLK>, 501 <&nsscc NSS_CC_PORT5_TX_CLK>; 502 clock-names = "mac", 503 "rx", 504 "tx"; 505 resets = <&nsscc PORT5_MAC_ARES>, 506 <&nsscc PORT5_RX_ARES>, 507 <&nsscc PORT5_TX_ARES>; 508 reset-names = "mac", 509 "rx", 510 "tx"; 511 }; 512 513 ethernet-port@6 { 514 reg = <6>; 515 phy-mode = "usxgmii"; 516 managed = "in-band-status"; 517 phy-handle = <&phy5>; 518 pcs-handle = <&pcs2_ch0>; 519 clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, 520 <&nsscc NSS_CC_PORT6_RX_CLK>, 521 <&nsscc NSS_CC_PORT6_TX_CLK>; 522 clock-names = "mac", 523 "rx", 524 "tx"; 525 resets = <&nsscc PORT6_MAC_ARES>, 526 <&nsscc PORT6_RX_ARES>, 527 <&nsscc PORT6_TX_ARES>; 528 reset-names = "mac", 529 "rx", 530 "tx"; 531 }; 532 }; 533 }; 534