xref: /linux/Documentation/devicetree/bindings/net/qcom,ethqos.yaml (revision cdd30ebb1b9f36159d66f088b61aee264e649d7a) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Ethernet ETHQOS device
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  dwmmac based Qualcomm ethernet devices which support Gigabit
14  ethernet (version v2.3.0 and onwards).
15
16allOf:
17  - $ref: snps,dwmac.yaml#
18
19properties:
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - qcom,qcs8300-ethqos
25          - const: qcom,sa8775p-ethqos
26      - items:
27          - enum:
28              - qcom,qcs615-ethqos
29          - const: qcom,sm8150-ethqos
30      - enum:
31          - qcom,qcs404-ethqos
32          - qcom,sa8775p-ethqos
33          - qcom,sc8280xp-ethqos
34          - qcom,sm8150-ethqos
35
36  reg:
37    maxItems: 2
38
39  reg-names:
40    items:
41      - const: stmmaceth
42      - const: rgmii
43
44  interrupts:
45    minItems: 1
46    items:
47      - description: Combined signal for various interrupt events
48      - description: The interrupt that occurs when Rx exits the LPI state
49      - description: The interrupt that occurs when HW safety error triggered
50
51  interrupt-names:
52    minItems: 1
53    items:
54      - const: macirq
55      - enum: [eth_lpi, sfty]
56      - const: sfty
57
58  clocks:
59    maxItems: 4
60
61  clock-names:
62    items:
63      - const: stmmaceth
64      - const: pclk
65      - const: ptp_ref
66      - enum:
67          - rgmii
68          - phyaux
69
70  iommus:
71    maxItems: 1
72
73  dma-coherent: true
74
75  phys: true
76
77  phy-names:
78    const: serdes
79
80required:
81  - compatible
82  - clocks
83  - clock-names
84  - reg-names
85
86unevaluatedProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/interrupt-controller/arm-gic.h>
91    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
92    #include <dt-bindings/gpio/gpio.h>
93
94    ethernet: ethernet@7a80000 {
95      compatible = "qcom,qcs404-ethqos";
96      reg = <0x07a80000 0x10000>,
97            <0x07a96000 0x100>;
98      reg-names = "stmmaceth", "rgmii";
99      clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
100      clocks = <&gcc GCC_ETH_AXI_CLK>,
101               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
102               <&gcc GCC_ETH_PTP_CLK>,
103               <&gcc GCC_ETH_RGMII_CLK>;
104      interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
105                   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
106                   <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
107      interrupt-names = "macirq", "eth_lpi", "sfty";
108
109      rx-fifo-depth = <4096>;
110      tx-fifo-depth = <4096>;
111
112      snps,tso;
113      snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
114      snps,reset-active-low;
115      snps,reset-delays-us = <0 10000 10000>;
116
117      pinctrl-names = "default";
118      pinctrl-0 = <&ethernet_defaults>;
119
120      phy-handle = <&phy1>;
121      phy-mode = "rgmii";
122      mdio {
123        #address-cells = <0x1>;
124        #size-cells = <0x0>;
125
126        compatible = "snps,dwmac-mdio";
127        phy1: phy@4 {
128          compatible = "ethernet-phy-ieee802.3-c22";
129          device_type = "ethernet-phy";
130          reg = <0x4>;
131
132          #phy-cells = <0>;
133        };
134      };
135    };
136