xref: /linux/Documentation/devicetree/bindings/net/qcom,ethqos.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Ethernet ETHQOS device
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  dwmmac based Qualcomm ethernet devices which support Gigabit
14  ethernet (version v2.3.0 and onwards).
15
16allOf:
17  - $ref: snps,dwmac.yaml#
18
19properties:
20  compatible:
21    enum:
22      - qcom,qcs404-ethqos
23      - qcom,sa8775p-ethqos
24      - qcom,sc8280xp-ethqos
25      - qcom,sm8150-ethqos
26
27  reg:
28    maxItems: 2
29
30  reg-names:
31    items:
32      - const: stmmaceth
33      - const: rgmii
34
35  interrupts:
36    minItems: 1
37    items:
38      - description: Combined signal for various interrupt events
39      - description: The interrupt that occurs when Rx exits the LPI state
40      - description: The interrupt that occurs when HW safety error triggered
41
42  interrupt-names:
43    minItems: 1
44    items:
45      - const: macirq
46      - enum: [eth_lpi, sfty]
47      - const: sfty
48
49  clocks:
50    maxItems: 4
51
52  clock-names:
53    items:
54      - const: stmmaceth
55      - const: pclk
56      - const: ptp_ref
57      - enum:
58          - rgmii
59          - phyaux
60
61  iommus:
62    maxItems: 1
63
64  dma-coherent: true
65
66  phys: true
67
68  phy-names:
69    const: serdes
70
71required:
72  - compatible
73  - clocks
74  - clock-names
75  - reg-names
76
77unevaluatedProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
83    #include <dt-bindings/gpio/gpio.h>
84
85    ethernet: ethernet@7a80000 {
86      compatible = "qcom,qcs404-ethqos";
87      reg = <0x07a80000 0x10000>,
88            <0x07a96000 0x100>;
89      reg-names = "stmmaceth", "rgmii";
90      clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
91      clocks = <&gcc GCC_ETH_AXI_CLK>,
92               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
93               <&gcc GCC_ETH_PTP_CLK>,
94               <&gcc GCC_ETH_RGMII_CLK>;
95      interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
96                   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
97                   <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
98      interrupt-names = "macirq", "eth_lpi", "sfty";
99
100      rx-fifo-depth = <4096>;
101      tx-fifo-depth = <4096>;
102
103      snps,tso;
104      snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
105      snps,reset-active-low;
106      snps,reset-delays-us = <0 10000 10000>;
107
108      pinctrl-names = "default";
109      pinctrl-0 = <&ethernet_defaults>;
110
111      phy-handle = <&phy1>;
112      phy-mode = "rgmii";
113      mdio {
114        #address-cells = <0x1>;
115        #size-cells = <0x0>;
116
117        compatible = "snps,dwmac-mdio";
118        phy1: phy@4 {
119          compatible = "ethernet-phy-ieee802.3-c22";
120          device_type = "ethernet-phy";
121          reg = <0x4>;
122
123          #phy-cells = <0>;
124        };
125      };
126    };
127