xref: /linux/Documentation/devicetree/bindings/net/qca,ar803x.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros AR803x PHY
8
9maintainers:
10  - Andrew Lunn <andrew@lunn.ch>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Heiner Kallweit <hkallweit1@gmail.com>
13
14description: |
15  Bindings for Qualcomm Atheros AR803x PHYs
16
17allOf:
18  - $ref: ethernet-phy.yaml#
19  - if:
20      properties:
21        compatible:
22          contains:
23            enum:
24              - ethernet-phy-id004d.d0c0
25
26    then:
27      properties:
28        reg:
29          const: 7  # This PHY is always at MDIO address 7 in the IPQ5018 SoC
30
31        resets:
32          items:
33            - description:
34                GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines.
35
36        qcom,dac-preset-short-cable:
37          description:
38            Set if this phy is connected to another phy to adjust the values for
39            MDAC and EDAC to adjust amplitude, bias current settings, and error
40            detection and correction algorithm to accommodate for short cable length.
41            If not set, DAC values are not modified and it is assumed the MDI output pins
42            of this PHY are directly connected to an RJ45 connector.
43          type: boolean
44
45properties:
46  compatible:
47    enum:
48      - ethernet-phy-id004d.d0c0
49
50  qca,clk-out-frequency:
51    description: Clock output frequency in Hertz.
52    $ref: /schemas/types.yaml#/definitions/uint32
53    enum: [25000000, 50000000, 62500000, 125000000]
54
55  qca,clk-out-strength:
56    description: Clock output driver strength.
57    $ref: /schemas/types.yaml#/definitions/uint32
58    enum: [0, 1, 2]
59
60  qca,disable-smarteee:
61    description: Disable Atheros SmartEEE feature.
62    type: boolean
63
64  qca,keep-pll-enabled:
65    description: |
66      If set, keep the PLL enabled even if there is no link. Useful if you
67      want to use the clock output without an ethernet link.
68
69      Only supported on the AR8031.
70    type: boolean
71
72  qca,disable-hibernation-mode:
73    description: |
74      Disable Atheros AR803X PHYs hibernation mode. If present, indicates
75      that the hardware of PHY will not enter power saving mode when the
76      cable is disconnected. And the RX_CLK always keeps outputting a
77      valid clock.
78    type: boolean
79
80  qca,smarteee-tw-us-100m:
81    description: EEE Tw parameter for 100M links.
82    $ref: /schemas/types.yaml#/definitions/uint32
83    minimum: 1
84    maximum: 255
85
86  qca,smarteee-tw-us-1g:
87    description: EEE Tw parameter for gigabit links.
88    $ref: /schemas/types.yaml#/definitions/uint32
89    minimum: 1
90    maximum: 255
91
92  vddio-supply:
93    description: |
94      RGMII I/O voltage regulator (see regulator/regulator.yaml).
95
96      The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
97      either connect this to the vddio-regulator (1.5V / 1.8V) or the
98      vddh-regulator (2.5V).
99
100      Only supported on the AR8031.
101
102  vddio-regulator:
103    type: object
104    description:
105      Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
106    $ref: /schemas/regulator/regulator.yaml
107    unevaluatedProperties: false
108
109  vddh-regulator:
110    type: object
111    description:
112      Dummy subnode to model the external connection of the PHY VDDH
113      regulator to VDDIO.
114    $ref: /schemas/regulator/regulator.yaml
115    unevaluatedProperties: false
116
117unevaluatedProperties: false
118
119examples:
120  - |
121    #include <dt-bindings/net/qca-ar803x.h>
122
123    ethernet {
124        #address-cells = <1>;
125        #size-cells = <0>;
126
127        phy-mode = "rgmii-id";
128
129        ethernet-phy@0 {
130            reg = <0>;
131
132            qca,clk-out-frequency = <125000000>;
133            qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
134
135            vddio-supply = <&vddio>;
136
137            vddio: vddio-regulator {
138                regulator-min-microvolt = <1800000>;
139                regulator-max-microvolt = <1800000>;
140            };
141        };
142    };
143  - |
144    #include <dt-bindings/net/qca-ar803x.h>
145
146    ethernet {
147        #address-cells = <1>;
148        #size-cells = <0>;
149
150        phy-mode = "rgmii-id";
151
152        ethernet-phy@0 {
153            reg = <0>;
154
155            qca,clk-out-frequency = <50000000>;
156            qca,keep-pll-enabled;
157
158            vddio-supply = <&vddh>;
159
160            vddh: vddh-regulator {
161            };
162        };
163    };
164  - |
165    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
166
167    mdio {
168        #address-cells = <1>;
169        #size-cells = <0>;
170
171        ge_phy: ethernet-phy@7 {
172            compatible = "ethernet-phy-id004d.d0c0";
173            reg = <7>;
174
175            resets = <&gcc GCC_GEPHY_MISC_ARES>;
176        };
177    };
178