xref: /linux/Documentation/devicetree/bindings/net/qca,ar803x.yaml (revision 26b8eb8a98c18b2ee4ea76d99fa2b2a5ccbc1b6c) 
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros AR803x PHY
8
9maintainers:
10  - Andrew Lunn <andrew@lunn.ch>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Heiner Kallweit <hkallweit1@gmail.com>
13
14description: |
15  Bindings for Qualcomm Atheros AR803x PHYs
16
17allOf:
18  - $ref: ethernet-phy.yaml#
19  - if:
20      properties:
21        compatible:
22          contains:
23            enum:
24              - ethernet-phy-id004d.d0c0
25
26    then:
27      properties:
28        reg:
29          const: 7  # This PHY is always at MDIO address 7 in the IPQ5018 SoC
30
31        clocks:
32          items:
33            - description: RX clock
34            - description: TX clock
35
36        clock-names:
37          items:
38            - const: rx
39            - const: tx
40
41        resets:
42          items:
43            - description:
44                GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines.
45
46        qcom,dac-preset-short-cable:
47          description:
48            Set if this phy is connected to another phy to adjust the values for
49            MDAC and EDAC to adjust amplitude, bias current settings, and error
50            detection and correction algorithm to accommodate for short cable length.
51            If not set, DAC values are not modified and it is assumed the MDI output pins
52            of this PHY are directly connected to an RJ45 connector.
53          type: boolean
54
55      required:
56        - clocks
57        - clock-names
58        - resets
59
60properties:
61  compatible:
62    enum:
63      - ethernet-phy-id004d.d0c0
64
65  qca,clk-out-frequency:
66    description: Clock output frequency in Hertz.
67    $ref: /schemas/types.yaml#/definitions/uint32
68    enum: [25000000, 50000000, 62500000, 125000000]
69
70  qca,clk-out-strength:
71    description: Clock output driver strength.
72    $ref: /schemas/types.yaml#/definitions/uint32
73    enum: [0, 1, 2]
74
75  qca,disable-smarteee:
76    description: Disable Atheros SmartEEE feature.
77    type: boolean
78
79  qca,keep-pll-enabled:
80    description: |
81      If set, keep the PLL enabled even if there is no link. Useful if you
82      want to use the clock output without an ethernet link.
83
84      Only supported on the AR8031.
85    type: boolean
86
87  qca,disable-hibernation-mode:
88    description: |
89      Disable Atheros AR803X PHYs hibernation mode. If present, indicates
90      that the hardware of PHY will not enter power saving mode when the
91      cable is disconnected. And the RX_CLK always keeps outputting a
92      valid clock.
93    type: boolean
94
95  qca,smarteee-tw-us-100m:
96    description: EEE Tw parameter for 100M links.
97    $ref: /schemas/types.yaml#/definitions/uint32
98    minimum: 1
99    maximum: 255
100
101  qca,smarteee-tw-us-1g:
102    description: EEE Tw parameter for gigabit links.
103    $ref: /schemas/types.yaml#/definitions/uint32
104    minimum: 1
105    maximum: 255
106
107  vddio-supply:
108    description: |
109      RGMII I/O voltage regulator (see regulator/regulator.yaml).
110
111      The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
112      either connect this to the vddio-regulator (1.5V / 1.8V) or the
113      vddh-regulator (2.5V).
114
115      Only supported on the AR8031.
116
117  vddio-regulator:
118    type: object
119    description:
120      Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
121    $ref: /schemas/regulator/regulator.yaml
122    unevaluatedProperties: false
123
124  vddh-regulator:
125    type: object
126    description:
127      Dummy subnode to model the external connection of the PHY VDDH
128      regulator to VDDIO.
129    $ref: /schemas/regulator/regulator.yaml
130    unevaluatedProperties: false
131
132unevaluatedProperties: false
133
134examples:
135  - |
136    #include <dt-bindings/net/qca-ar803x.h>
137
138    ethernet {
139        #address-cells = <1>;
140        #size-cells = <0>;
141
142        phy-mode = "rgmii-id";
143
144        ethernet-phy@0 {
145            reg = <0>;
146
147            qca,clk-out-frequency = <125000000>;
148            qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
149
150            vddio-supply = <&vddio>;
151
152            vddio: vddio-regulator {
153                regulator-min-microvolt = <1800000>;
154                regulator-max-microvolt = <1800000>;
155            };
156        };
157    };
158  - |
159    #include <dt-bindings/net/qca-ar803x.h>
160
161    ethernet {
162        #address-cells = <1>;
163        #size-cells = <0>;
164
165        phy-mode = "rgmii-id";
166
167        ethernet-phy@0 {
168            reg = <0>;
169
170            qca,clk-out-frequency = <50000000>;
171            qca,keep-pll-enabled;
172
173            vddio-supply = <&vddh>;
174
175            vddh: vddh-regulator {
176            };
177        };
178    };
179  - |
180    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
181    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
182
183    mdio {
184        #address-cells = <1>;
185        #size-cells = <0>;
186
187        ge_phy: ethernet-phy@7 {
188            compatible = "ethernet-phy-id004d.d0c0";
189            reg = <7>;
190
191            clocks = <&gcc GCC_GEPHY_RX_CLK>,
192                     <&gcc GCC_GEPHY_TX_CLK>;
193            clock-names = "rx", "tx";
194            resets = <&gcc GCC_GEPHY_MISC_ARES>;
195        };
196    };
197