xref: /linux/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PD692x0 Power Sourcing Equipment controller
8
9maintainers:
10  - Kory Maincent <kory.maincent@bootlin.com>
11
12allOf:
13  - $ref: pse-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - microchip,pd69200
19      - microchip,pd69210
20      - microchip,pd69220
21
22  reg:
23    maxItems: 1
24
25  disable-ports-gpios:
26    description: GPIO pin to disable PoE on all ports
27    maxItems: 1
28
29  vdd-supply:
30    description: Regulator that provides 3.3V VDD power supply.
31
32  vdda-supply:
33    description: Regulator that provides 3.3V VDDA power supply.
34
35  managers:
36    type: object
37    additionalProperties: false
38    description:
39      List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
40      have 4 or 8 physical ports according to the chip version. No need to
41      specify the SPI chip select as it is automatically detected by the
42      PD692x0 PSE controller. The PSE managers have to be described from
43      the lowest chip select to the greatest one, which is the detection
44      behavior of the PD692x0 PSE controller. The PD692x0 support up to
45      12 PSE managers which can expose up to 96 physical ports. All
46      physical ports available on a manager have to be described in the
47      incremental order even if they are not used.
48
49    properties:
50      "#address-cells":
51        const: 1
52
53      "#size-cells":
54        const: 0
55
56    required:
57      - "#address-cells"
58      - "#size-cells"
59
60    patternProperties:
61      "^manager@[0-9a-b]$":
62        type: object
63        additionalProperties: false
64        description:
65          PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
66          ports.
67
68        properties:
69          reg:
70            description:
71              Incremental index of the PSE manager starting from 0, ranging
72              from lowest to highest chip select, up to 11.
73            maxItems: 1
74
75          "#address-cells":
76            const: 1
77
78          "#size-cells":
79            const: 0
80
81          vmain-supply:
82            description: Regulator that provides 44-57V VMAIN power supply.
83
84          vaux5-supply:
85            description: Regulator that provides 5V VAUX5 power supply.
86
87          vaux3p3-supply:
88            description: Regulator that provides 3.3V VAUX3P3 power supply.
89
90        patternProperties:
91          '^port@[0-7]$':
92            type: object
93            additionalProperties: false
94
95            properties:
96              reg:
97                maxItems: 1
98
99            required:
100              - reg
101
102        required:
103          - reg
104          - "#address-cells"
105          - "#size-cells"
106
107required:
108  - compatible
109  - reg
110  - pse-pis
111
112unevaluatedProperties: false
113
114examples:
115  - |
116    i2c {
117      #address-cells = <1>;
118      #size-cells = <0>;
119
120      ethernet-pse@3c {
121        compatible = "microchip,pd69200";
122        reg = <0x3c>;
123
124        managers {
125          #address-cells = <1>;
126          #size-cells = <0>;
127
128          manager0: manager@0 {
129            reg = <0>;
130            #address-cells = <1>;
131            #size-cells = <0>;
132            vmain-supply = <&pse1_supply>;
133
134            phys0: port@0 {
135              reg = <0>;
136            };
137
138            phys1: port@1 {
139              reg = <1>;
140            };
141
142            phys2: port@2 {
143              reg = <2>;
144            };
145
146            phys3: port@3 {
147              reg = <3>;
148            };
149          };
150
151          manager@1 {
152            reg = <1>;
153            #address-cells = <1>;
154            #size-cells = <0>;
155
156            phys4: port@0 {
157              reg = <0>;
158            };
159
160            phys5: port@1 {
161              reg = <1>;
162            };
163
164            phys6: port@2 {
165              reg = <2>;
166            };
167
168            phys7: port@3 {
169              reg = <3>;
170            };
171          };
172        };
173
174        pse-pis {
175          #address-cells = <1>;
176          #size-cells = <0>;
177
178          pse_pi0: pse-pi@0 {
179            reg = <0>;
180            #pse-cells = <0>;
181            pairset-names = "alternative-a", "alternative-b";
182            pairsets = <&phys0>, <&phys1>;
183            polarity-supported = "MDI", "S";
184            vpwr-supply = <&manager0>;
185          };
186          pse_pi1: pse-pi@1 {
187            reg = <1>;
188            #pse-cells = <0>;
189            pairset-names = "alternative-a";
190            pairsets = <&phys2>;
191            polarity-supported = "MDI";
192            vpwr-supply = <&manager0>;
193          };
194        };
195      };
196    };
197