xref: /linux/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml (revision 8e07e0e3964ca4e23ce7b68e2096fe660a888942) 
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP TJA11xx PHY
8
9maintainers:
10  - Andrew Lunn <andrew@lunn.ch>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Heiner Kallweit <hkallweit1@gmail.com>
13
14description:
15  Bindings for NXP TJA11xx automotive PHYs
16
17allOf:
18  - $ref: ethernet-phy.yaml#
19
20patternProperties:
21  "^ethernet-phy@[0-9a-f]+$":
22    type: object
23    additionalProperties: false
24    description: |
25      Some packages have multiple PHYs. Secondary PHY should be defines as
26      subnode of the first (parent) PHY.
27
28    properties:
29      reg:
30        minimum: 0
31        maximum: 31
32        description:
33          The ID number for the child PHY. Should be +1 of parent PHY.
34
35      nxp,rmii-refclk-in:
36        type: boolean
37        description: |
38          The REF_CLK is provided for both transmitted and received data
39          in RMII mode. This clock signal is provided by the PHY and is
40          typically derived from an external 25MHz crystal. Alternatively,
41          a 50MHz clock signal generated by an external oscillator can be
42          connected to pin REF_CLK. A third option is to connect a 25MHz
43          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
44          as input or output according to the actual circuit connection.
45          If present, indicates that the REF_CLK will be configured as
46          interface reference clock input when RMII mode enabled.
47          If not present, the REF_CLK will be configured as interface
48          reference clock output when RMII mode enabled.
49          Only supported on TJA1100 and TJA1101.
50
51    required:
52      - reg
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    mdio {
59        #address-cells = <1>;
60        #size-cells = <0>;
61
62        tja1101_phy0: ethernet-phy@4 {
63            reg = <0x4>;
64            nxp,rmii-refclk-in;
65        };
66    };
67  - |
68    mdio {
69        #address-cells = <1>;
70        #size-cells = <0>;
71
72        tja1102_phy0: ethernet-phy@4 {
73            reg = <0x4>;
74            #address-cells = <1>;
75            #size-cells = <0>;
76
77            tja1102_phy1: ethernet-phy@5 {
78                reg = <0x5>;
79            };
80        };
81    };
82