xref: /linux/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml (revision a34b0e4e21d6be3c3d620aa7f9dfbf0e9550c19e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2021-2024 NXP
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
9
10maintainers:
11  - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
12
13description:
14  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
15  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
16  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
17  interface over Pinctrl device or the output can be routed
18  to the embedded SerDes for SGMII connectivity.
19
20properties:
21  compatible:
22    oneOf:
23      - const: nxp,s32g2-dwmac
24      - items:
25          - enum:
26              - nxp,s32g3-dwmac
27              - nxp,s32r45-dwmac
28          - const: nxp,s32g2-dwmac
29
30  reg:
31    items:
32      - description: Main GMAC registers
33      - description: GMAC PHY mode control register
34
35  nxp,phy-sel:
36    $ref: /schemas/types.yaml#/definitions/phandle-array
37    items:
38      - items:
39          - description: phandle to the GPR syscon node
40          - description: offset of PHY selection register
41    description:
42      This phandle points to the GMAC_0_CTRL_STS register which controls the
43      GMAC_0 configuration options.  The register lets you select the PHY
44      interface and the PHY mode.  It also controls if the FTM_0 or FTM_1
45      FlexTimer Modules connect to GMAC_0.
46
47  interrupts:
48    maxItems: 1
49
50  interrupt-names:
51    const: macirq
52
53  clocks:
54    items:
55      - description: Main GMAC clock
56      - description: Transmit clock
57      - description: Receive clock
58      - description: PTP reference clock
59
60  clock-names:
61    items:
62      - const: stmmaceth
63      - const: tx
64      - const: rx
65      - const: ptp_ref
66
67required:
68  - clocks
69  - clock-names
70
71allOf:
72  - $ref: snps,dwmac.yaml#
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/interrupt-controller/arm-gic.h>
79    #include <dt-bindings/interrupt-controller/irq.h>
80    #include <dt-bindings/phy/phy.h>
81    bus {
82      #address-cells = <2>;
83      #size-cells = <2>;
84
85      ethernet@4033c000 {
86        compatible = "nxp,s32g2-dwmac";
87        reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
88              <0x0 0x4007c004 0x0 0x4>;    /* GMAC_0_CTRL_STS */
89        nxp,phy-sel = <&gpr 0x4>;
90        interrupt-parent = <&gic>;
91        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
92        interrupt-names = "macirq";
93        snps,mtl-rx-config = <&mtl_rx_setup>;
94        snps,mtl-tx-config = <&mtl_tx_setup>;
95        clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
96        clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
97        phy-mode = "rgmii-id";
98        phy-handle = <&phy0>;
99
100        mtl_rx_setup: rx-queues-config {
101          snps,rx-queues-to-use = <5>;
102        };
103
104        mtl_tx_setup: tx-queues-config {
105          snps,tx-queues-to-use = <5>;
106        };
107
108        mdio {
109          #address-cells = <1>;
110          #size-cells = <0>;
111          compatible = "snps,dwmac-mdio";
112
113          phy0: ethernet-phy@0 {
114            reg = <0>;
115          };
116        };
117      };
118    };
119